Semiconductor memory device and data output buffer thereof

Details Semiconductor memory device and data output buffer thereof Semiconductor memory device and data output buffer thereof

2000-06-05

2001-03-06

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S078000, C365S230060

Reexamination Certificate

active

06198650

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device and a data output buffer thereof in which its layout area can be optimized.
DESCRIPTION OF THE PRIOR ART
In a conventional semiconductor memory device, input/output pads and the surrounding circuits are arranged centering around memory cell array blocks. Input/output pads and output drivers are typically arranged at the top and data output buffers are separately arranged at the bottom of each memory cell array block, with two signal lines connected from a data output buffer to an output driver and extending therebetween from top to bottom. Such an arrangement is inefficient in terms of layout because the two signal lines must pass between adjacent memory cell array blocks.
FIG. 1
is a block diagram showing a layout of the conventional semiconductor memory device, comprising memory cell array blocks
10
-
1
,
10
-
2
, . . . ,
10
-(n-
1
),
10
-n, sense amplifiers
12
-
1
,
12
-
2
, . . . ,
12
-(n-
1
),
12
-n, data output buffers
20
-
1
,
20
-
2
, . . . ,
20
-(n-
1
),
20
-n consisting of first and second registers
14
-
1
,
14
-
2
, . . . ,
14
-(n-
1
),
14
-n, and output drivers
16
-
1
,
16
-
2
, . . . ,
16
-(n-
1
),
16
-n, and input/output pads
18
-
1
,
18
-
2
, . . . ,
18
-(n-
1
),
18
-n.
The conventional semiconductor memory device layout shown in
FIG. 1
will be described in further detail.
It may be seen that the memory cell array blocks
10
-
1
,
10
-
2
, . . . ,
10
-(n-
1
),
10
-n are arranged in the device's center, top-to-bottom, with the sense amplifiers
12
-
1
,
12
-
2
, . . . ,
12
-(n-
1
),
12
-n and first and second registers
14
-
1
,
14
-
2
, . . . ,
14
-(n-
1
),
14
-n arranged below the memory cell array blocks, with input/output pads
18
-
1
,
18
-
2
, . . . ,
18
-(n-
1
),
18
-n and output drivers
16
-
1
,
16
-
2
, . . . ,
16
-(n-
1
),
16
-n arranged above the memory cell array blocks, and with data line pairs DOU, DOD arranged between the laterally adjacent memory cell array blocks.
As shown in
FIG. 1
, in order to minimize the length of the signal line between the sense amplifiers
12
-
1
,
12
-
2
, . . . ,
12
-(n-l),
12
-n and the first and second registers
14
-
1
,
14
-
2
, . . . ,
14
-(n-
1
),
14
-n and the length of the signal line between the input/output pads
18
-
1
,
18
-
2
, . . . ,
18
-(n-
1
),
18
-n and the output drivers
16
-
1
,
16
-
2
, . . . ,
16
-(n-
1
),
16
-n, the first and second registers
14
-
1
,
14
-
2
, . . . ,
14
-(n-
1
),
14
-n are arranged adjacent to the sense amplifiers
12
-
1
,
12
-
2
, . . . ,
12
-(n-
1
),
12
-n and the output drivers
16
-
1
,
16
-
2
, . . . ,
16
-(n-
1
),
16
-n are arranged adjacent to the input/output pads
18
-
1
,
18
-
2
, . . . ,
18
-(n-
1
),
18
-n. Of course, it is preferable that the first and second registers
14
-
1
,
14
-
2
, . . . ,
14
-(n-
1
),
14
-n are arranged adjacent to the output drivers
16
-
1
,
16
-
2
, . . . ,
16
-(n-
1
),
16
-n. However, the output drivers
16
-
1
,
16
-
2
, . . . ,
16
-(n-
1
),
16
-n are arranged adjacent to the input/output pads
18
-
1
,
18
-
2
,...,
18
-(n-
1
),
18
-n because the additional resistance/capacitance between the output drivers
16
-
1
,
16
-
2
, . . . ,
16
-(n-
1
),
16
-n and the pads
18
-
1
,
18
-
2
, . . . ,
18
-(n-
1
),
18
-n exerts a worse influence upon an operational speed of the semiconductor memory device than that between the first and second registers
14
-
1
,
14
-
2
, . . . ,
14
-(n-
1
),
14
-n and the output drivers
16
-
1
,
16
-
2
, . . . ,
16
-(n-
1
),
16
-n.
Thus, the layout shown in
FIG. 1
is typical of the layout of a semiconductor memory device.
FIG. 2
is a circuit diagram of a data output buffer of the conventional semiconductor memory device, comprising first and second registers
100
,
200
and an output driver
300
. The reference numerals of the first and second registers
100
,
200
and driver
300
are different from those of the corresponding registers and driver of FIG.
1
.
The first register
100
comprises a multiplexer MUX
1
including PMOS transistors P
1
, P
2
and NMOS transistor N
1
; a multiplexer MUX
2
including PMOS transistors P
3
, P
4
and NMOS transistor N
2
; and a latch L
1
including inverters I
3
,
14
. The register
200
comprises a clocked CMOS inverter CI
1
including PMOS transistors P
5
, P
6
and NMOS transistors N
3
, N
4
; a clocked CMOS inverter CI
2
including inverter I
5
, PMOS transistors P
7
, P
8
and NMOS transistors N
5
, N
6
; a latch L
2
including inverters I
6
, I
7
; and NAND gates NA
1
, NA
2
. The output driver
300
comprises NMOS transistors N
7
, N
8
.
The operation of the circuit shown in
FIG. 2
will be described in further detail.
The register
100
receives sense a pair of complementary output signals SASb, SAS from the sense amplifier and generates a pair of data output signals DATAAb, DATAA to latch the data. The multiplexers MUX
1
, MUX
2
allow the PMOS transistors P
1
, P
2
and NMOS transistor N
2
to be turned-on in response to the sense output signal pair SASb, SAS of “high” level and “low” level to thereby generate the data output signal pair DATAAb, DATAA of “high” level and “low” level. Also, the multiplexers MUX
1
, MUX
2
allow the NMOS transistor N
1
and PMOS transistors P
3
, P
4
to be turned-on in response to the sense output signal pair SASb, SAS of “low” level and “high” level, thereby generating the data output signal pair DATAAb, DATAA of “low” level and “high” level. The latch L
1
latches the data output signal pair DATAAb, DATAA to output them.
The register
200
receives a pair of data output signals DATAAb, DATAA to invert them in response to a clock control signal KDATA of “high” level and generates a pair of data output signals DATAC, DATACb to latch the data.
The clocked CMOS inverters CI
1
, CI
2
serve to turn on the PMOS transistors P
5
, P
7
and NMOS transistors N
4
, N
6
in response to the clock control signal KDATA of “high” level. When the data output signal pair DATAAb, DATAA of “high” level and “low” level are input, the NMOS transistor N
3
and PMOS transistor P
8
are turned-on, thereby generating the data output signal pair DATAC, DATACb of “low” level and “high” level. Alternatively, when the data output signal pair DATAAb, DATAA of “low” level and “high” level are input, the PMOS transistor P
6
and NMOS transistor N
5
are turned-on, thereby generating the data output signal pair DATAC, DATACb of “high” level and “low” level. The latch having the inverters I
6
, I
7
latches the data output signal pair DATAC, DATACb. The NAND gates NA
1
, NA
2
and inverters I
8
, I
9
generate the data output signal pair DATAC, DATACb as a pair of data output signals DOU, DOD in response to an output enable signal OE of “high” level. The NAND gates NA
1
, NA
2
and inverters I
8
, I
9
also generate the data output signal pair DOU, DOD of “low” level in response to the output enable signal OE of “low” level.
The output driver
300
allows the NMOS transistor N
7
to be turned-on in response to the data output signal pair DOU, DOD of “high” level and “low” level to generate an output signal XI
0
of “high” level. The output driver
300
alternatively allows the NMOS transistor N
8
to be turned-on in response to the data output signal pair DOU, DOD of “low” level and “high” level to generate an output signal XI
0
of “low” level.
FIG. 3
is a timing diagram illustrating the operation of the data output buffer shown in FIG.
2
. If the clock signal XCLK is input into the semiconductor memory device, the clock control signal is generated. And, during the first, second fourth read command cycles I, II, IV, if an inversion data output enable signal XOEb of “low” level for outputting data is input into the semiconductor memory device, the signal is inverted and buffered, thereby generating a data output enable signal OE of “high” level. Then, the data output buffer is operated to generate the data output signal

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