Semiconductor memory device and arrangement method thereof

Details Semiconductor memory device and arrangement method thereof Semiconductor memory device and arrangement method thereof

2007-11-13

2007-11-13

Phung, Anh (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S156000, C365S051000

Reexamination Certificate

active

11225221

ABSTRACT:
A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

REFERENCES:
patent: 6980462 (2005-12-01), Ramesh et al.
patent: 08-063957 (1996-03-01), None
patent: 09-253806 (1997-09-01), None
patent: 2003-085989 (2003-03-01), None
patent: 10-2001-0016800 (2001-03-01), None
English language abstract of Japanese Publication No. 2003-085989.
English language abstract of Japanese Publication No. 08-063957.
English language abstract of Japanese Publication No. 09-253806.

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