Semiconductor memory device and a reading method thereof

Details Semiconductor memory device and a reading method thereof Semiconductor memory device and a reading method thereof

1998-03-18

1999-03-16

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

36523006, 365193, 365196, 365233, G11C 800

Patent

active

058838511

ABSTRACT:
In a semiconductor memory device, there is provided a column detecting circuit for generating a detection signal DETIO when respective voltage levels on a pair of I/O lines IO and IOB are developed into predetermined voltage levels which can be sensed as a valid data by external circuitry. Thereafter, a block selecting circuit and a sensing control signal generating circuit are respectively disabled by the detection signals DETIO and DETIOB causing a bit line precharge operation to be performed during a reading operation Thus, the sensing consumed by sense amplifiers during the reading operation period is reduced. In addition, since the bit line precharge operation is performed during the reading operation period, the bit line precharge time is reduced.

REFERENCES:
patent: 5276649 (1994-01-01), Hoshita et al.
patent: 5715208 (1998-02-01), Casper et al.
patent: 5719814 (1998-02-01), Ishikawa

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