Semiconductor memory device and a method of using the same

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – With extended latchup current level

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257133, 257139, 257140, 257141, H01L 2974

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active

054970113

ABSTRACT:
In this semiconductor device, first, fifth and fourth impurity regions of a second conductivity type are formed on a main surface of a semiconductor layer of a first conductivity type with a predetermined space between each other. Second and third impurity regions of the first conductivity type are formed on the main surface of the first impurity region with a predetermined space between each other. A second gate electrode is formed between the second and third impurity regions. A first gate electrode is formed between the third impurity region and the semiconductor layer. A cathode electrode is connected to the third impurity region, and a short-circuit electrode is connected to first and second impurity regions. The first and fifth impurity regions are electrically short-circuited. Thereby, in the on state of the thyristor operation, the transistor including the second gate electrode can be off, whereby an entire hole current in the semiconductor layer forms a base current of one of the bipolar transistors, resulting in reduction of the holding current. Since the second gate electrode is provided independently from the first gate electrode, the gate length of the second gate electrode can be reduced, so that the on-resistance can be reduced, and thus the maximum controllable current can be increased.

REFERENCES:
patent: 5091766 (1992-02-01), Terashima
patent: 5155569 (1992-10-01), Terashima

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