Semiconductor memory device and a method for generating a...

Details Semiconductor memory device and a method for generating a... Semiconductor memory device and a method for generating a...

2002-12-13

2004-05-11

Mai, Son (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030

Reexamination Certificate

active

06735147

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having a plurality of memory cell array blocks, each of which has 2
K
+a (k and a are an integer, respectively) word lines, and a method for generating a block selection signal for selecting said word lines.
2. Description of the Related Art
In general, a semiconductor memory device includes a plurality of memory cell array blocks and each of the memory cell array blocks has 2
k
(k is an integer) word lines. Data is read out and written into a memory cell array block which is selected in response to a corresponding block selection signal.
FIG. 1
is a block diagram of a semiconductor memory device with a plurality of memory cell array blocks.
FIG. 1
illustrates a conventional method of generating a block selection signal for selecting one memory cell array block from a plurality of memory cell array blocks. As shown in
FIG. 1
, the semiconductor memory device includes 16 memory cell array blocks BLK
1
-BLK
16
and each of the blocks has 512 (2
k
, k is 9) word lines WL
1
-WL
512
.
In
FIG. 1
, row address signals RA
12
B, RA
11
B, RA
10
B, and RA
9
B represent inverted signals of address signals RA
12
, RA
11
, RA
10
, and RA
9
, respectively. Block selection signals for selecting one of the memory cell array blocks BLK
1
-BLK
16
are generated by decoding 4-bit row address signals RA
12
-RA
9
. Word line selection signals for selecting a word line out of 512 word lines in a memory cell array block are generated by decoding 9-bit row address signals RA
0
-RA
8
.
A conventional method for generating the block selection signals for selecting each of the 16 memory cell array blocks BLK
1
-BLK
16
will be described below.
A block selection signal for selecting the first block BLK
1
is generated when the row address signals RA
12
B, RA
11
B, RA
10
B and RA
9
B are all at a logic “high” level. A block selection signal for selecting the second block BLK
2
is generated when the row address signals RA
12
B, RA
11
B, RA
10
B and RA
9
are all at a logic “high” level. A block selection signal for selecting the third block BLK
3
is generated when the row address signals RA
12
B, RA
11
B, RA
10
and RA
9
B are all at a logic “high” level. A block selection signal for selecting the fourth block BLK
4
is generated when the row address signals RA
12
B, RA
11
B, RA
10
and RA
9
are all in a logic “high” level. Similarly, a block selection signal for selecting the sixteenth block BLK
16
is generated when the row address signals RA
12
, RA
11
, RA
10
and RA
9
have a logic “high” level.
FIG. 2
is a schematic block diagram showing the memory cell array block from
FIG. 1
in more detail. Each of the memory cell array blocks BLK
1
-BLK
16
includes a plurality of pairs of bit lines BL
1
-BL
1
B, BL
2
-BL
2
B, BL
3
-BL
3
B, etc.
Between each of the memory cell array blocks BLK
1
-BLK
16
, a pre-charge circuit
14
-
1
is arranged at the right end of bit line pairs BL
1
-BL
1
B, BL
2
-BL
2
B and a pre-charge circuit
14
-
2
is arranged at the left end of bit line pairs BL
1
-BL
1
B, BL
2
-BL
2
B.
Bit line isolation circuits
12
-
1
are arranged on the left side of a corresponding pre-charge circuit
14
-
1
and bit line isolation circuits
12
-
2
are arranged on the right side of a corresponding pre-charge circuit
14
-
2
. Bit line isolation circuits
12
-
1
are comprised of two NMOS transistors N
1
and N
2
. Bit line isolation circuits
12
-
2
are comprised of two NMOS transistors N
3
and N
4
.
Sense amplifiers
10
-
1
,
10
-
12
are connected to each of the corresponding bit line pairs by being interposed between the corresponding pre-charge circuit
14
-
1
or
14
-
2
and the bit line isolation circuit
12
-
1
or
12
-
2
. The sense amplifier
10
-
1
is arranged on the left side of the first memory cell array block BLK
1
and is coupled to the the bit line isolation circuit
12
-
1
by the bit line pair belonging to the first memory cell array block BLK
1
. The sense amplifier
10
-
12
is arranged on the right side of the sixteenth memory cell array block BLK
16
and is coupled to the the bit line isolation circuit
12
-
2
by the bit line pair belonging to the sixteenth memory cell array block BLK
16
.
The sense amplifier
10
-
12
is arranged in a space between adjacent memory cell array blocks BLK
1
-BLK
16
by being interposed between the corresponding bit line isolation circuits
12
-
1
,
12
-
2
. The sense amplifier
10
-
12
is shared by two memory cell array blocks which are arranged on the left side thereof and on the right side thereof, respectively. Each of the sense amplifiers
10
-
12
is coupled to each pair of the bit lines BL
1
-BL
1
B, BL
2
-BL
2
B, . . . , in two memory cell array blocks arranged on either side of the sense amplifier
10
-
12
.
As shown in FIG.
1
and
FIG. 2
, the semiconductor memory device in accordance with the conventional art has 2
k
memory cell arrays.
In
FIG. 2
, signals ISO
1
-ISO
16
are the block selection signals for selecting one of the memory cell array blocks BLK
1
-BLK
16
.
Operation of the memory cell array shown in
FIG. 2
is as follows:
During pre-charging operation, the pre-charge circuits
14
-
1
,
14
-
2
pre-charge the pairs of bit lines BL
1
-BL
1
B, BL
2
-BL
2
B, etc.
After a word line WL
1
is selected, charge sharing occurs between the pairs of bit lines BL
1
-BL
1
B, BL
2
-BL
2
B, etc, that are connected to the memory cells that are in turn coupled to the selected word line WL
1
and the capacitors belonging to the corresponding memory cells.
After that, the signal ISO
1
is generated with a “high” logic level when a block selection signal for selecting the memory cell block BLK
1
is generated. As a result, the NMOS transistors N
1
-N
4
of the bit line isolation circuits
12
-
1
,
12
-
2
are turned on and the sense amplifiers
10
-
1
,
10
-
12
are operated to amplify data signals from the pairs of bit lines.
As shown in FIG.
1
and
FIG. 2
, seventeen amplifying circuits for amplifying data signals produced by the pairs of bit lines are needed for the semiconductor memory device having 16 memory cell array blocks BLK
1
-BLK
16
. For example, fifteen of the seventeen amplifying circuits are arranged in every corresponding space between adjacent memory cell array blocks BLK
1
-BLK
16
and two amplifying circuits are arranged beside the outermost memory cell array blocks BLK
1
, BLK
16
.
That is, a conventional semiconductor memory device requires seventeen data amplifying circuits, to such an extent that the memory cell array parts dominates a large area of the semiconductor substrate. Accordingly, it is difficult to reduce the chip size including the semiconductor memory device therein.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device having a reduced lay-out area dominated by the memory cell array.
It is another object of the present invention to provide a method of generating a block selection signal for a semiconductor memory device having 2
k
+a word lines in each memory cell array block.
In accordance with one aspect of the present invention, there is provided a semiconductor memory device including a memory cell array having 2
n
(n is an integer) groups of memory cell array blocks, each of the group having m (m is an integer) memory cell array blocks, each of the memory cell array blocks having 2
K
+a (K and a are integers) word lines, and a block selection signal generating circuit for generating a block selection signal for selecting one of the memory cell array blocks by decoding a plurality of row address signals.
The block selection signal generating circuit comprises a first-step-block-selection signal generating circuit for generating a first-step-block-selection signal for selecting one group out of the 2
n
groups, a second-step-block-selection signal generating circuit for generating a second-step-block-selection signal for selecting one memory cell array block in the every group, a third-step-

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