Semiconductor memory device allowing reduction of an area loss

Details Semiconductor memory device allowing reduction of an area loss Semiconductor memory device allowing reduction of an area loss

2003-02-03

2004-11-16

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Powering

C365S189090, C365S189110

Reexamination Certificate

active

06819619

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device allowing reduction of an area loss in a power supply circuit, which generates an internal voltage within the semiconductor memory device.
2. Description of the Background Art
Owing to advances in semiconductor technology, it is now possible to produce a logic-mixed memory, which includes a logic circuit and a DRAM (Dynamic Random Access Memory) in a single chip. This can significantly improve a data transfer rate between the logic circuit and the DRAM.
Referring to
FIG. 34
, a logic-mixed memory
700
includes a DRAM
800
, SRAMs (Static Random Access Memories)
810
and
820
, a logic circuit
830
and pads
840
.
DRAM
800
and SRAMs
810
and
820
are memories for storing data. Logic circuit
830
controls input/output of data to and from DRAM
800
and SRAMs
810
and
820
. Pads
840
are terminals and are arranged in a peripheral portion for inputting and/or outputting a power supply voltage, control signals and data to and/or from logic-mixed memory
700
.
In logic-mixed memory
700
, logic circuit
830
rapidly transmits data and others to and from the memories, i.e., DRAM
800
and SRAMs
810
and
820
.
Referring to
FIG. 35
, DRAM
800
includes memory cell arrays
801
and
802
, a row column decoder
803
, data buses
804
and
805
, a control circuit
806
, a power supply circuit
807
and a test circuit
808
.
Each of memory cell arrays
801
and
802
includes a plurality of memory cells, a plurality of word lines, a plurality of bit line pairs, a plurality of sense amplifiers provided corresponding to the respective bit line pairs, a plurality of equalize circuits provided corresponding to the respective bit line pairs, and others. The plurality of memory cells are arranged in rows and columns. The plurality of word lines are arranged in the row directions of the plurality of memory cells arranged in rows and columns. The plurality of bit line pairs are arranged in the column direction of the plurality of memory cells arranged in rows and columns.
Row column decoder
803
is arranged between memory cell arrays
801
and
802
. Row column decoder
803
decodes an externally applied address, and activates the word line or the bit line pair designated by the decoded address.
Data buses
804
and
805
are lines for transmitting the data to and from the plurality of memory cells included in memory cell arrays
801
and
802
. Control circuit
806
controls operations such as input/output of data with respect to the plurality of memory cells.
Power supply circuit
807
generates an internal voltage based on an external power supply voltage, which is externally supplied, and supplies the internal voltage thus generated to memory cell arrays
801
and
802
as well as peripheral circuits such as control circuit
806
.
Test circuit
808
conducts tests on DRAM
800
.
Referring to
FIG. 36
, power supply circuit
807
includes a Vbb generating circuit
850
, a reference voltage generating circuit
860
, a voltage down converter
870
, Vcc/2 generating circuits
880
and
890
, and a VPP generating circuit
900
.
Vbb generating circuit
850
is formed of a level converter
851
, a control circuit
852
, a detecting circuit
853
, an oscillator
854
and a pump circuit
855
. Level converter
851
receives power supply voltages from nodes N
1
and N
2
. Node N
1
supplies the power supply voltage, e.g., of 1.5 V. Node N
2
supplies the power supply voltage, e.g., of 3.3 V. Level converter
851
receives a control signal such as a test mode signal TM, and converts the voltage level forming test mode signal TM thus received from 1.5 V to 3.3 V. Level converter
851
provides test mode signal TM subjected to the level conversion to control circuit
852
.
Control circuit
852
receives the power supply voltage of 3.3 V from node N
2
. Control circuit
852
controls detecting circuit
853
based on test mode signal TM received from level converter
851
. More specifically, when test mode signal TM is at an H (logical high) level, control circuit
852
activates or deactivates detecting circuit
853
for conducting various tests. When test mode signal TM is at an L (logical low) level, control circuit
852
activates detecting circuit
853
.
Detecting circuit
853
receives the power supply voltage of 3.3 V from node N
2
. Detecting circuit
853
detects a negative voltage Vbb when a signal BIASL received from a current source
861
of reference voltage generating circuit
860
is at H-level, and provides the detection signal of negative voltage Vbb to oscillator
854
.
Oscillator
854
receives the power supply voltage of 3.3 V from node N
2
. Oscillator
854
generates a clock CLK, which has a phase corresponding to the logical level of the detection signal received from detecting circuit
853
, and provides clock CLK thus generated to pump circuit
855
.
Pump circuit
855
receives a power supply voltage of 3.3 V from node N
2
. Pump circuit
855
pumps carriers to generate negative voltage Vbb of 0.7 V in synchronization with clock CLK received from oscillator
854
.
As described above, Vbb generating circuit
850
is driven by the power supply voltage of 3.3 V received from node N
2
, and generates negative voltage Vbb of −0.7 V for providing it to memory cell arrays
801
and
802
.
Reference voltage generating circuit
860
includes current source
861
and a voltage generating circuit
862
. Current source
861
receives the power supply voltage of 3.3 V from node N
2
. Based on the power supply voltage of 3.3 V received from node N
2
, current source
861
generates a voltage VII as well as signals BIASL and ICONST formed of a voltage in a linear operation region of the MOS transistor, provides voltage VII and signal ICONST thus generated to voltage generating circuit
862
, and provides signal BIASL to detecting circuit
853
of Vbb generating circuit
850
, voltage down converter
870
and VPP generating circuit
900
. Signal ICONST is formed of a maximum voltage in the linear motion region of the MOS transistor. Signal BIASL is formed of a minimum voltage in the linear motion region of the MOS transistor.
Voltage generating circuit
862
receives voltage VII and signal ICONST from current source
861
, and operates based on voltage VII and signal ICONST thus received to generate a reference voltage VrefS of 1.5 V and provide it to voltage down converter
870
and VPP generating circuit
900
.
As described above, reference voltage generating circuit
860
is driven by the power supply voltage of 3.3 V received from node N
2
, and generates reference voltage VrefS of 1.5 V lower than the power supply voltage.
Voltage down converter
870
includes a level converter
871
, a control circuit
872
, differential amplifier circuits
873
and
876
, P-channel MOS transistors
874
and
877
, and N-channel MOS transistors
875
and
878
. Level converter
871
receives the power supply voltage of 1.5 V from node N
1
, and receives the power supply voltage of 3.3 V from node N
2
. Level converter
871
receives control signals such as test mode signal TM, sense amplifier enable signal SAE or the like, and converts the voltage level of received test mode signal TM or sense amplifier enable signal SAE from 1.5 V to 3.3 V. Level converter
871
provides test mode signal TM or sense amplifier enable signal SAE at the converted level to control circuit
872
.
Control circuit
872
receives the power supply voltage of 3.3 V from node N
2
. Control circuit
872
receives test mode signal TM or sense amplifier enable signal SAE from level converter
871
, and provides received test mode signal TM or sense amplifier enable signal SAE to a gate terminal of N-channel MOS transistor
875
. In the test mode of DRAM
800
, control circuit
872
receives test mode signal TM at H- or L-level corresponding to contents of the intended test, and provides received test mode signal TM at H- or L-level to the gate terminal

Affiliated with

Also associated with

Rating

Semiconductor memory device allowing reduction of an area loss does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device allowing reduction of an area loss, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device allowing reduction of an area loss will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3283619