Semiconductor memory device allowing reduction in current...

Details Semiconductor memory device allowing reduction in current... Semiconductor memory device allowing reduction in current...

2000-09-11

2001-11-20

Nelms, David (Department: 2818)

Static information storage and retrieval

Powering

C365S189110, C365S189090, C365S230060

Reexamination Certificate

active

06320810

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly, a semiconductor device including a Voltage Down Converter (VDC).
2. Description of the Background Art
External power supply potentials ext.Vdd supplied to semiconductor chips have been lowered in accordance with demands for reduction in power consumption of systems employing the chips. Although the external power supply potential ext.Vdd has been lowered, problems relating to reliability and others may practically occur if the external power supply potential is used as an operation power supply potential of transistors within the chip without converting it. In view of this, an internal power supply potential Vdd lower than external power supply potential ext.Vdd is generally generated within the chip for using it as the operation power supply potential of transistors.
FIG. 12
is a block diagram showing a structure of a synchronous dynamic random access memory (SDRAM)
501
, which is an example of a conventional semiconductor chip.
Referring to
FIG. 12
, SDRAM
501
includes four banks, which have a total storage capacity of 256 megabits and can operate independently of each other. In SDRAM
501
, read/write operations are performed in synchronization with a clock signal CLK which is externally supplied thereto. For performing an intended operation, a command determined by a combination of control signals /RAS, /CAS and /WE is applied thereto. Also, SDRAM
501
is externally supplied with appropriate or necessary signals such as a control signal /CS instructing chip selection as well as a control signal CKE instructing whether clock signal CLK is to be taken into SDRAM
501
or not.
SDRAM
501
further includes a power supply potential generating circuit
510
which is externally supplied with an external power supply potential ext.Vdd, and issues an internal power supply potential Vdd after lowering the voltage. Power supply potential generating circuit
510
includes a VDC control circuit
532
which receives row-related bank activating signals from row decoders and word drivers
10
#
0
-
10
#
3
provided corresponding to the respective memory array banks, and issues signals ICL, ICM and ICS, a Vref generating circuit
534
which generates a reference potential Vref, and a voltage down converter (VDC)
536
which receives reference potential Vref, and issues power supply potential Vdd by lowering external power supply potential ext.Vdd to the same level as reference potential Vref at a response speed corresponding to signals ICL, ICM and ICS.
VDC control circuit
532
issues signals ICL, ICM and ICS based on the active state of the bank and the command. VDC
536
operates with a response speed controlled by signals ICL, ICM and ICS, and supplies a current from a node supplied with external power supply potential ext.Vdd to a node issuing internal power supply potential Vdd so that internal power supply potential Vdd may be equal to reference potential Vref.
FIG. 13
is a circuit diagram showing a structure of VDC
536
shown in FIG.
12
.
Referring to
FIG. 13
, VDC
536
includes a shifter circuit
602
which receives reference potential Vref and internal power supply potential Vdd, and shifts the input level, a comparator
604
which receives signals REF and SIG issued from shifter circuit
602
, and makes a comparison between them, and a driver
606
which operates in accordance with the output of comparator
604
to supply a current from the node supplied with external power supply potential ext.Vdd to the node issuing internal power supply potential Vdd.
Shifter circuit
602
includes an NOR circuit
612
which receives a signal ACT and a signal CKEI, a P-channel MOS transistor
618
which is connected between a node receiving external power supply potential ext.Vdd and a node N
61
, and receives on its gate the output of NOR circuit
612
, an N-channel MOS transistor
620
which is connected between nodes N
61
and N
62
, and receives reference potential Vref on its gate, an N-channel MOS transistor
622
which is connected between node N
62
and a ground node, and has a gate connected to a node N
63
, an N-channel MOS transistor
624
which is connected between nodes N
61
and N
63
, and receives internal power supply potential Vdd on its gate, and an N-channel MOS transistor
626
which has a gate and a drain connected to node N
63
, and also has a source connected to the ground node. A signal REF is issued from node N
62
of shifter circuit
602
, and a signal SIG is issued from node N
63
.
Comparator
604
includes a P-channel MOS transistor
628
which is connected between a node supplied with external power supply potential ext.Vdd and node N
64
, and has a gate connected to a node N
65
, an N-channel MOS transistor
630
which is connected between nodes N
64
and N
66
, and has a gate receiving signal REF, a P-channel MOS transistor
632
which has a source coupled to external power supply potential ext.Vdd, and has a gate and a drain connected to a node N
65
, an N-channel MOS transistor
634
which is connected between nodes N
65
and N
66
, and has a gate receiving signal SIG, and N-channel MOS transistors
636
,
638
and
640
which are connected in parallel between node N
66
and the ground node, and have gates receiving ICL, ICM and ICS, respectively.
Comparator
604
issues from its node N
64
a signal DO for controlling a current supplied from the driver.
Driver
606
includes a P-channel MOS transistor
642
which is connected between a node supplied with external power supply potential ext.Vdd and a node issuing internal power supply potential Vdd, and has a gate receiving signal DO.
Typical operation specifications of the SDRAM are called “PC
100
”, and the following description will be given by way of example on an SDRAM conforming the PC
100
.
FIG. 14
is an operation waveform diagram showing waveforms of external signals in the write operation of SDRAM
501
.
Referring to
FIG. 14
, these waveforms show an operation in the case where each of a RAS-CAS delay time tRCD and a row precharge time tRP is equal to 3 cycles, and a burst length BL is 4.
At time t
1
and therefore at a rising edge of clock signal CLK, the device is supplied with a command ACT[
0
] activating row-related portions in bank
0
. The command is supplied together with a bank address, and a number inside square brackets following each command represents the bank address.
A combination of signals A
0
-A
12
is applied as a row address X for selecting one word line WL, and at the same time, a combination of signals BA
0
and BA
1
is applied as a bank address which designates bank
0
.
At time t
4
after three cycles, a command WRITE[
0
] for performing writing on word line WL, which is already active, is supplied in response to the rising edge of clock signal CLK. At the same time, column address Y formed of a combination of signals A
0
-A
9
is applied, and the bank address is also applied. Command WRITE is determined by the combination of control signals /CS, /RAS, /CAS and /WE. For four cycles from time t
4
to time t
7
, write data D
0
-D
3
are applied in accordance with a combination of externally applied signals DQ
0
-DQ
15
, and are written into the memory cells.
At time t
8
, a command PRE[
0
] for resetting word lines WL in active bank
0
is externally supplied to the device. Command PRE is applied as a combination of control signals /CS, /RAS, /CAS and /WE. For reliably writing the data into the memory cells, a time tWR must be kept between writing of last data D
3
and subsequent input of command PRE[
0
]. In the foregoing manner, the data can be written into a specific bank.
When the same bank is to be accessed subsequently, a time equal to row precharge time tRP or more is required before starting the access.
When the operation shown in
FIG. 14
is performed, a current consumption with internal power supply potential Vdd of the SDRAM varies with time.
FIG. 15
is a schematic waveform diagra

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