Semiconductor memory device allowing high density structure...

Details Semiconductor memory device allowing high density structure... Semiconductor memory device allowing high density structure...

2002-04-22

2004-04-20

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S189110

Reexamination Certificate

active

06724679

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor memory device, and particularly to semiconductor memory devices, in which interconnections between a plurality of banks are reduced in number, timing of input/output of data to and from a plurality of banks is adjusted, a burn-in test using a plurality of power supply voltages at different levels can be performed, and/or an internal voltage activating word lines can be stably supplied.
2. Description of the Background Art
Referring to
FIG. 45
, a conventional semiconductor memory device
1000
such as a DRAM (Dynamic Random Access Memory) includes banks
1010
-
1013
and predecoders
1014
-
1017
.
Each of banks
1010
-
1013
includes a plurality of memory cells disposed in rows and columns, a plurality of bit line pairs, a plurality of word lines, a column decoder, a row decoder and a sense amplifier.
Predecoders
1014
-
1017
are disposed corresponding to banks
1010
-
1013
, respectively. Predecoders
1014
and
1016
are disposed between banks
1010
and
1012
, and predecoders
1015
and
1017
are disposed between banks
1011
and
1013
. Predecoders
1014
-
1017
produce predecode signals for selecting banks
1010
-
1013
based on the address input through address terminals, respectively, and output the predecode signals thus produced to banks
1010
-
1013
, respectively. Further, predecoders
1014
-
1017
receive addresses AYA<
3
:
0
>, AYB<
3
:
0
>, AYC<
3
:
0
> and AYD<
3
:
0
>, and output received addresses AYA<
3
:
0
>, AYB<
3
:
0
>, AYC<
3
:
0
> and AYD<
3
:
0
> to corresponding banks
1010
-
1013
, respectively.
Banks
1010
-
1013
are selected by the predecode signals applied from predecoders
1014
-
1017
. In the selected bank (one of banks
1010
-
1013
), data is input/output to or from the memory cells designated by the addresses received from corresponding one of predecoders
1014
-
1017
.
As described above, the conventional semiconductor memory device is provided with the plurality of predecoders corresponding to the plurality of banks, respectively. The plurality of predecoders are concentratedly arranged in one position.
Referring to
FIG. 46
, a conventional semiconductor memory device
1100
such as an SDRAM (Synchronous DRAM), in which data is input/output to and from the memory cells in synchronization with a clock, includes banks
1010
-
1013
, a driver
1018
and a repeater
1019
. Banks
1010
-
1013
are the same as those already described.
Driver
1018
receives a clock CLK from an external terminal, and produces a clock CLKQ used for output of data from received clock CLK. Driver
1018
outputs clock CLKQ thus produced to repeater
1019
.
Repeater
1019
is disposed in a central portion of semiconductor memory device
1100
. Repeater
1019
supplies clock CLKQ received from driver
1018
to banks
1010
-
1013
. In this case, repeater
1019
supplies clock CLKQ to banks
1010
-
1013
through paths of the substantially same length. Thereby, each of banks
1010
-
1013
can output the data substantially in accordance with the same timing as the other banks.
Banks
1010
-
1013
output the data, which is read from the memory cells, to the input/output terminals (not shown) in synchronization with clock CLKQ received from repeater
1019
.
In the conventional semiconductor memory device, as described above, the timing of data output from the plurality of banks is adjusted or controlled by supplying a clock produced by a driver to the respective banks via the one repeater.
For inputting or outputting data to or from each of the plurality of memory cells disposed in rows and columns, the word line disposed in the row direction must be activated, and an internally boosted voltage prepared by boosting the power supply voltage is used for this activation of the word line. A pump capacitor is used for boosting the power supply voltage to the internally boosted voltage.
FIG. 47
is a plan showing a pump capacitor, and shows, on an enlarged scale, a region A of the pump capacitor. Aluminum interconnections
1022
-
1027
are disposed at a first layer under aluminum interconnections
1020
and
1021
at a second layer. Bit lines BL (not shown) are disposed under aluminum interconnections
1022
-
1027
at the first layer, and transfer gates TG (not shown) are disposed under bit lines BL. Further, a field diffusion layer FL (not shown) is disposed under transfer gates TG. Insulating layers are interposed between aluminum interconnections
1020
and
1021
and aluminum interconnections
1022
-
1027
, between aluminum interconnections
1022
-
1027
and bit lines BL, between bit lines BL and transfer gates TG, and between transfer gates TG and field diffusion layer FL.
Bit lines BL are connected through contact holes to transfer gates TG and field diffusion layer FL, and aluminum interconnections
1022
-
1028
at the first layer are connected to bit lines BL through contact holes
1029
,
1030
,
1033
,
1034
,
1035
,
1038
,
1039
,
1042
and
1043
. Aluminum interconnection
1020
at the second layer is connected to aluminum interconnection
1026
at the first layer through contact holes
1036
. Aluminum interconnection
1021
at the second layer is connected through contact holes
1031
,
1032
,
1040
and
1041
to aluminum interconnections
1024
,
1025
,
1027
and
1028
at the first layer.
Accordingly, aluminum interconnection
1020
at the second layer is connected to transfer gate TG, which forms one of two electrodes forming the pump capacitor, and aluminum interconnection
1021
at the second layer is connected to field diffusion layer FL forming the other electrode of the pump capacitor. Thereby, the internally boosted voltage boosted by the pump capacitor is supplied via aluminum interconnections
1020
and
1021
at the second layer to the word line drivers (not shown), and the word line driver supplies the internally boosted voltage to the word line, which is designated by a row address applied from the row decoder, so that the word line designated by the row address is activated.
FIG. 48
is a plan showing one of the plurality of pump capacitors. A bit line
1051
is disposed on a transfer gate
1045
with an insulating layer (not shown) therebetween, and bit line
1051
is connected to transfer gate
1045
via eighteen contact holes
1046
. Twelve contact holes
1047
are provided for connecting bit line
1051
to the aluminum interconnection (not shown), which is located at the first layer, and is formed on bit line
1051
with the insulating layer (not shown) therebetween.
Field diffusion layer
1044
is formed over transfer gate
1045
, and bit lines
1049
,
1050
,
1054
and
1055
are arranged over a portion of the field diffusion layer not overlapping with transfer gate
1045
. Each of bit lines
1049
and
1050
is connected to field diffusion layer
1044
through fourteen contact holes
1053
, and each of bit lines
1054
and
1055
is connected to field diffusion layer
1044
via fourteen contact holes
1057
. Twenty contact holes
1052
are provided for connecting bit lines
1049
and
1050
to aluminum interconnections (not shown), which are located at the first layer, and are formed on bit lines
1049
and
1050
with the insulating layer (not shown) therebetween. Twenty contact holes
1056
are provided for connecting bit lines
1054
and
1055
to aluminum interconnections (not shown), which are located at the first layer, and are formed on bit lines
1054
and
1055
with the insulating layer (not shown) therebetween.
Referring to
FIG. 49
, conventional semiconductor memory devices
1000
and
1100
include internal voltage generating circuits
1060
-
1065
, terminals
1066
-
1077
, switches
1078
-
1083
, a control circuit
1084
and a switching circuit
1085
.
Internal voltage generating circuits
1060
-
1062
lower the power supply voltage to generate internal voltages VREFS, VREFP and VREFD, respectively. Internal voltage generating circuit
1063
lowers the power supply voltage to gene

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