Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-12-23
2004-10-19
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189011
Reexamination Certificate
active
06807101
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, to a configuration of a data reading section in a non-volatile semiconductor memory device storing information in a non-volatile manner. More particularly, the present invention relates to a semiconductor memory device capable of correctly reading data even when a characteristic of a memory cell is deteriorated.
2. Description of the Background Art
A non-volatile semiconductor memory device storing data in a non-volatile manner has been known as one of semiconductor memory devices. A memory cell of the non-volatile semiconductor memory device is constituted of one transistor. Data is stored by accumulating electric charges in a charge accumulating region electrically isolated from the surroundings of the memory cell transistor to change a threshold voltage of the memory cell transistor. Since electric charges (referred to as charges simply hereinafter) are stored in a charge accumulating region isolated electrically from the surroundings, even if a power supply is cut off, the charges continue being accumulated in the charge accumulating region and data can be stored in a non-volatile manner.
FIG. 20
is a diagram schematically showing a sectional structure of a conventional non-volatile memory cell. In
FIG. 20
, the non-volatile memory cell includes: impurity regions
901
and
902
formed spaced apart from each other on a surface of a semiconductor substrate region
900
; a charge accumulating region
903
formed above a channel forming region between impurity regions
901
and
902
; and a control gate electrode
904
formed above charge accumulating region
903
. Charge accumulating region
903
is constituted of a floating gate made of polysilicon or the like, or of a nitride film. In a case where charge accumulating region
903
is constituted of a nitride film, oxide films are formed between charge accumulating region
903
and control gate electrode
904
, and between charge accumulating region
903
and substrate region
900
.
In a construction of a non-volatile memory cell shown in
FIG. 20
, accumulation of charges (an electron is indicated by e−) into charge accumulating region
903
is performed in the following way. That is, impurity region
901
is supplied with a high voltage in the range from 4 V to 5 V, for example, while impurity region
902
is maintained at ground voltage level. Control gate electrode
904
is applied with a voltage in the range from 5 V to 6 V.
In this state, a channel region
905
is formed at the surface of the substrate between impurity regions
901
and
902
and a current I flows from impurity region
901
to impurity region
902
. Current I flowing in channel region
905
is accelerated by a high electric field formed in the vicinity of impurity region
901
(drain region) to form hot electrons. The hot electrons are accelerated in a direction toward charge accumulating region
903
by a high voltage applied to control gate electrode
904
and injected into charge accumulating region
903
. In a case where charge accumulating region
903
is formed of polysilicon or the like, injected electrons move over an entire of charge accumulating region
903
. In a case where charge accumulating region
903
is constituted of a nitride film or the like, electrons trapped in charge accumulating region
903
do not move over a long distance to be localized in the vicinity of impurity region
901
.
A state where electrons have been injected into charge accumulating region
903
is hereinafter referred to as written state (programmed state). In the written state, since electrons are accumulated in charge accumulating region
903
, the memory cell transistor has a high threshold voltage (provided that the memory cell transistor is of an N-channel type).
FIG. 21
is a diagram showing an example of applied voltages to a memory cell when electrons are extracted from charge accumulating region
903
. There are various ways for erase operations. In
FIG. 21
, there are shown applied voltages employed in a substrate erasure method in which electrons are ejected into a substrate region.
In
FIG. 21
, when electrons are extracted from charge accumulating region
903
, control gate electrode
904
is supplied with, for example, a negative voltage of −5 V and impurity regions
901
and
902
are supplied with a voltage in the range from 5 to 6 V. In this case, substrate region
900
is supplied with a voltage at a level similar to the voltage of impurity regions
901
and
902
. In this state, electrons (e−) accumulated in charge accumulating region
903
are ejected to substrate region
900
through a Fouler-Nordheim (FN) tunnel current. This state is usually called an erased state, where a threshold voltage decreases.
As an erase operation for a non-volatile memory cell, there are available a method in which channel hot holes are injected into charge accumulating region
903
, and a method in which electrons are extracted from charge accumulating region
903
to gate electrode
904
and others.
By a quantity of charges stored in charge accumulating region
903
, as shown in
FIGS. 20 and 21
, a threshold voltage of the memory cell transistor changes, and the threshold voltage is correlated with data. Therefore, since a threshold voltage changes consecutively according to a quantity of electric charges stored in charge accumulating region
903
, the non-volatile memory cell can store multi-valued data.
FIG. 22
is a diagram schematically showing applied voltages when data is read from the non-volatile memory cell. In
FIG. 22
, control gate electrode
904
is supplied with a read voltage Vread, while impurity region
901
is supplied with ground voltage. Impurity region
902
is supplied with a bit current Ib
1
. Read voltage Vread is set to an intermediate voltage level between threshold voltages in erased state and written state, or a voltage level higher than a threshold voltage in written state.
When read voltage Vread is set to an intermediate value between a threshold voltage in erased state and that in written state, the memory cell transistor in erased state is turned on, while the memory cell transistor in written state is turned off. Substantially no bit current Ib
1
flows through the memory cell in the written state.
When read voltage Vread is set to a voltage level higher than a threshold voltage in the written state, a current flows through the memory cell in any of erased state and written state. Threshold voltages in erased state and written state are different from each other, and therefore, a channel resistance of the memory cell transistor is different according to whether the memory cell transistor is in the erased state or in the written state, and a current flowing through the memory cell transistor is made different in magnitude, accordingly. Therefore, by detecting a quantity of current through a bit line, a state of the memory cell, or stored data can be detected.
FIG. 23
is a diagram schematically showing data storage regions in a case where charge accumulating region
903
is constituted of a nitride film. In
FIG. 23
, in a case where charge accumulating region
903
is constituted of a nitride film, an oxide film
908
is formed between control gate electrode
904
and charge accumulating region
903
and an oxide film
909
is formed between charge accumulating region
903
and semiconductor substrate region
900
. In charge accumulating region
903
, there are formed data storage regions BTR and BTL. In a case where charge accumulating region
903
is made of a nitride film, an electron mobility is very low, and the data storage regions are formed being localized in charge accumulating region
903
. When electrons are injected into data storage region BTR (right bit region), a current I is conducted from impurity region
902
to impurity region
901
. In this state, hot electrons are generated by a high drain electric field formed in the vicinity of impurity region
902
Kato Hiroshi
Ohtani Jun
Ooishi Tsukasa
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