Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-12-27

2004-06-29

Tran, M. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S239000

Reexamination Certificate

active

06757210

ABSTRACT:

TECHNICAL FIELD
The present disclosure relates to semiconductor memory devices, and more particularly, to a semiconductor memory device configured to share a local I/O (input/output) line.
BACKGROUND
A conventional memory core structure minimizes distance between memory cell arrays to maximize memory cell efficiency. In particular, the conventional memory core structure requires a maximum of 16 bits of data outputs, and thus shares a local I/O line.
On the other hand, a high speed memory such as a double data rate (DDR), a DDR-II and a graphic memory outputs a maximum of 32 bits of data. The high speed memory is required to have high speed burst operation, and thus the core must read data as many as a number of the bursts in advance. This function is a prefetch function. The DDR uses 2 bit prefetch and the DDR-II uses 4 bit prefetch. For example, the X16 DDR-II operates at 400MHz with 4 bursts, uses 4 bit prefetch, and reads 64 bits of data by one core access.
However, because the conventional core structure gradually increases an operation speed and widens a bandwidth, it cannot share the local I/O line. As a result, a spatial efficiency cannot be achieved.
SUMMARY OF THE DISCLOSURE
A semiconductor memory device configured to share a local I/O line by sequentially outputting data in a pipeline form is disclosed herein.
The semiconductor memory device includes: a memory cell array including a plurality of memory cells; a plurality of bit line sense amplifiers configured to sense and to amplify data stored in the plurality of memory cells; a plurality of bit lines configured to transmit the data stored in the plurality of memory cells to the plurality of bit line sense amplifiers, respectively; a plurality of bit line dividing circuits configured to selectively divide the plurality of bit lines; and a plurality of column selecting circuits configured to sequentially transmit the data amplified by the plurality of bit line sense amplifiers to corresponding I/O lines.


REFERENCES:
patent: 5053997 (1991-10-01), Miyamato et al.
patent: 5404338 (1995-04-01), Murai et al.
patent: 5764590 (1998-06-01), Iwamoto et al.
patent: 6160754 (2000-12-01), Suh

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3318748