Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2003-08-06

2004-12-28

Lam, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230080, C365S189050

Reexamination Certificate

active

06836446

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to a semiconductor memory device. More specifically, it pertains to a semiconductor memory device which reads stored data by switching output signals from plural sense amplifiers.
BACKGROUND OF THE INVENTION
A method in which the number of memory cells connected to bit lines is increased is presented as a relatively simple method for increasing the storage capacity of a semiconductor memory device, such as an SRAM. However, the capacitive constituents of the memory cells increase with the number of memory cells, and the capacitive constituents of the bit lines also increase as they become longer, creating the problem that the memory cells driving the bit lines are more heavily loaded. Because the driving capability of a transistor utilized for a memory cell is subject to limits imposed by the type of manufacturing process, the use of said method to increase the storage capacity is thereby also limited.
Thus, a method in which the number of bit lines is increased is widely used as another method for increasing the storage capacity.
FIG. 7
is a block diagram of an example configuration of a semiconductor memory device in which the number of bit lines is increased light times.
The semiconductor memory device shown in
FIG. 7
has memory cell array
1
, bit line selector circuit
2
, and sense amplifier
3
.
Memory cell array
1
has memory cells arranged in rows and columns, and the memory cells in respective columns are connected to bit line pairs (BL
0
, BL
0
Z) through (BL
7
, BL
7
Z). Although not shown specifically, memory cells in each row are connected to a common word line, and access is gained to memory cells connected to an activated word line via applicable bit line pair (BL
0
, BL
0
Z) through (BL
7
, BL
7
Z).
Bit line selector circuit
2
selects among bit line pairs (BL
0
, BL
0
Z) through (BL
7
, BL
7
Z) according to bit line selection signal SEL
0
Z through SEL
7
Z and outputs the signals on the selective bit line pair to sense amplifier
3
.
In the example illustrated in
FIG. 7
, bit line selector circuit
2
has p-type MOS transistors
2
-
0
through
2
-
7
and p-type MOS transistors
2
-
0
Z through
2
-
7
Z.
Bit lines BL
0
through BL
7
on one side of the bit line pairs are connected to common output line N, and bit lines BL
0
Z through BL
7
Z on the other side are connected to common output line NZ. In addition, p-type MOS transistors
2
-
0
through
2
-
7
are inserted into the connecting lines between bit lines BL
0
through BL
7
and output line N, and p-type MOS transistors
2
-
0
Z through
2
-
7
Z are inserted into the connecting lines between bit lines BL
0
Z through BL
7
Z and output line NZ. Bit line selection signals SEL
0
Z through SEL
7
Z are input to the gates of p-type MOS transistors
2
-
0
through
2
-
7
, and bit line selection signals SEL
0
Z through SEL
7
Z are input also to the gates of p-type MOS transistors
2
-
0
Z through
2
-
7
Z.
Sense amplifier
3
amplifies the small difference in voltage of bit line pair selected by bit line selector circuit
2
during a read of data stored in the memory cells. The value of the data stored in a memory cell is identified on the basis of said amplified voltage difference.
In the case of the semiconductor memory device in
FIG. 7
, to read the data stored in the memory cells, one of bit line selection signals SEL
0
Z through SEL
7
Z is set to a low level according to the address to be read. Thus, the p-type MOS transistor which received the low-level bit line selection signal through its gate conducts, and the signal from one of bit line pairs (BL
0
, BL
0
Z) through (BL
7
, BL
7
Z) is output to sense amplifier from output line N and NZ
3
via the conducting p-type MOS transistor.
On the other hand, when a word line of memory cell array
1
is activated in response to said read address, bit line pair (BL
0
, BL
0
Z) through (BL
7
, BL
7
Z) is driven by the memory cells connected to the activated word line, and the voltage difference corresponding to the data stored in the memory cell is generated on bit line pair (BL
0
, BL
0
Z) through (BL
7
, BL
7
Z).
Sense amplifier
3
amplifies the voltage difference on the single bit line pair from the bit line pairs selected by bit line selector circuit
2
, and the value of the stored data is identified on the basis of said voltage difference.
Thus, with the semiconductor memory device in
FIG. 7
, the memory capacity can be increased by selecting I bit line pair from the plural bit line pairs using the selector circuit. However, the aforementioned method has the problem that the selector circuit itself used for bit line selection loads the memory cells. For example, the capacitive constituents of p-type MOS transistors
2
-
1
through
2
-
7
of bit line selector circuit
2
are also added to the capacitive constituents of the memory cells as the load of bit line BL
0
of the semiconductor memory device in FIG.
7
. As the number of the bit line pairs is further increased, the load due to the capacitive constituents of the transistors of the selector circuit increases.
Thus, as the number of the bit line pairs is increased, often the method is used in which plural bit line selector circuits and plural sense amplifiers are used, with the output signals being switched.
FIG. 8
is a block diagram illustrating an example configuration of a semiconductor memory device in which the number of the bit lines is increased by 16 times using 2-bit line selector circuits and sense amplifiers.
The semiconductor memory device shown in
FIG. 8
has memory cell array
1
, bit line selector circuits
2
_A and
2
_B, sense amplifiers
3
_A and
3
_B, latch circuits
4
_A and
4
_B, and switch circuits
5
_A and
5
_B.
Memory cell array
1
A has plural memory cells arranged in rows and columns, and 16 columns of memory cells are connected to 16 bit line pairs. Said 16 bit line pairs are divided into 2 blocks, each comprising 8 pairs, one of the 2 blocks (referred to as Block A hereinafter) is connected to bit line selector circuit
2
_A, and the other (referred to as Block B hereinafter) is connected to bit line selector circuit
2
_B.
In addition, like memory cell array
1
, memory cells in each row are connected to a common word line, and the memory cells are accessed by activating specific word lines and bit line pairs.
Bit line selector circuit
2
_A selects 1 bit line pair out of the 8 bit line pairs of Block A according to bit line selection signal SB and outputs the signals on the selected bit line pair to sense amplifier
3
_A.
Bit line selector circuit
2
_B selects 1 bit line pair out of the 8 bit line pairs of Block B according to bit line selection signal SB and outputs the signals on the selected bit line pair to sense amplifier
3
_B.
Said bit line selector circuits
2
_A and
2
_B can be configured using a circuit similar to bit selector circuit
2
of the semiconductor memory device in FIG.
7
.
Sense amplifier
3
_A amplifies the small difference in the voltage of bit line pair selected by bit line selector circuit
2
_A when enable signal EN (not shown) changes from low level to high level during a read of the stored data. Since said voltage difference is amplified, either output terminal SA_A or SAZ_A is set to the high level, and the other is set to the low level.
Sense amplifier
3
_B amplifies the small difference in the voltage of bit line pair selected by bit line selector circuit
2
_B when enable signal EN (not shown) changes from the low level to the high level during a read of stored data. Since said voltage difference is amplified, either output terminal SA_B or SAZ_B is set to the high level, and the other is set to the low level.
Said amplification operation is performed by one of the 2 sense amplifiers
3
_A or
3
B, whichever is selected according to block selection signal line SM.
Latch circuit
4
_A outputs a high-level or low-level signal SL_A to switch circuit
5
_A according to the levels of signals of output terminals SA_A and SAZ_A of sense amplifier
3
_A. When output terminal

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