Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2003-01-31
2004-09-21
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S071000, C365S230060
Reexamination Certificate
active
06795328
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a technique capable of attaining both high-speed access and low current consumption in an inactive state.
2. Description of Related Art
As the digital system becomes more and more high in its function, both large memory storage and high speed of data access are being required of a semiconductor memory device.
For the speed-up of data access it is necessary to attain the speed-up of a sense amplifier which amplifies read memory cell data. To this end it is necessary to improve the drivability of a driver which supplies electric power to the sense amplifier. The sense amplifier is constructed so as to be supplied with electric power and activated at the time of performing an amplifying operation and not supplied with electric power in an inactive state thereof. The driver is provided with a driver-dedicated MOS transistor which provides a connection between the sense amplifier and a power supply, and it turns conductive in the amplifying operation to supply electric power to the sense amplifier. Improving the drivability for ensuring as sufficient supply of electric power to the sense amplifier means decreasing ON-resistance while the driver is conductive. Therefore, it is necessary to use a driver-dedicated MOS transistor having a sufficient gate width W and sufficient current drivability. Further, it is necessary to ensure a sufficient wiring region for the driver-dedicated MOS transistor.
With an increase of capacity, the number of sense amplifiers used increases, resulting in that the layout region of a group of sense amplifiers supplied with electric power from one driver-dedicated MOS transistor becomes very wide and a positional relation between the driver-dedicated MOS transistor and the sense amplifiers differs greatly sense amplifier by sense amplifier. For ensuring a high-speed performance of the sense amplifier located at the remotest point it is necessary to use a driver-dedicated MOS transistor having a large gate width W.
In view of the above-mentioned circumstances there heretofore has been proposed a dispersive layout of driver-dedicated MOS transistors in which driver-dedicated MOS transistors are embedded dispersively in a sense amplifier layout region so that each driver-dedicated MOS transistor is allocated to a predetermined number of sense amplifiers. This method attempts to secure a gate width W having sufficient current drivability and the speed-up of access while minimizing an increase in the layout area of driver-dedicated MOS transistors.
Recently, portable devices which realize high function digital systems have become popular. In a portable device, for improving a continuous operation time characteristic in battery drive, it is absolutely necessary to decrease the power consumption in a stand-by state. In a stand-by state it is absolutely necessary to decrease the leakage current of MOS transistors, etc.
As a typical leakage current in MOS transistor, a drain current is conceivable which is known as a so-called sub-threshold characteristic (tailing characteristic) and which flows when the gate-source voltage bias is below the threshold voltage. With a lowering of the threshold voltage, the sub-threshold characteristic (tailing characteristic) becomes more and more conspicuous. If a comparison is made in terms of a predetermined voltage bias of below the threshold voltage, the lower the threshold voltage,the more flows the drain current. If the threshold voltage lowers to below 0.4V or so, it becomes impossible to completely cut off the drain current even with no voltage bias applied between the gate and the source. The drain current in this state is particularly called tailing current.
However, the conventional dispersive layout method intends to ensure sufficient current drivability and high-speed access while minimizing an increase of the layout area of driver-dedicated MOS transistors, so that the overall gate width W of driver-dedicated MOS transistors becomes large. In addition, a source terminal is connected to a power supply and a large voltage is applied between the drain and the source. Coupled with these points, at a low threshold voltage there flows much tailing current, thus giving rise to the problem that it is impossible to attain a low current consumption in a stand-by state.
Further, ensuring sufficient current supply capability of a driver-dedicated MOS transistor which is necessary for the speed-up of data access and decreasing the tailing current of a driver-dedicated MOS transistor which is necessary for attaining a low current consumption in a stand-by state, are in a trade-off relation. Therefore, in the field of portable devices having a high-function digital system, it is important to adjust both characteristics. In the prior art, however, it is impossible to make an adjustment for the simultaneous attainment of both ensuring sufficient current drivability of a driver-dedicated MOS transistor and decreasing the tailing current, such as the adjustment of transistor size, adjustment of voltage bias condition, and adjustment of threshold voltage. This arises a problem in mounting a high-function digital system in a portable device.
SUMMARY OF THE INVENTION
The present invention has been accomplished for solving the above-mentioned problems and it is an object of the invention to provide a semiconductor memory device having a driver transistor for the supply of electric power and capable of diminishing leakage current in an inactive state while ensuring sufficient power supply capability for a sense amplifier in an inactive state.
For achieving the above-mentioned object, according to first aspect of the present invention, there is provided a semiconductor memory device comprising: at least one sense amplifier disposed in at least one sense amplifier layout region correspondingly to a wiring pitch of bit lines; and at least one driver-dedicated MOS transistor for the supply of electric power to the sense amplifier, the driver-dedicated MOS transistor being disposed in the sense amplifier layout region in such a manner that its gate width is oriented perpendicularly to the wiring direction of the bit lines, wherein a power terminal of the sense amplifier and a drain terminal of the driver-dedicated MOS transistor are connected with each other through a low resistance wiring layer.
In the semiconductor memory device according to the first aspect, the driver-dedicated MOS transistor is disposed in the sense amplifier layout region where the sense amplifier is disposed, in such a manner that its gate width direction is perpendicular to the wiring direction of bit lines, and electric power is fed from the drain terminal of the driver-dedicated MOS transistor to the power terminal of the sense amplifier through a low resistance wiring layer.
For the supply of electric power to the sense amplifier with sufficient power supply capability, the driver-dedicated MOS transistor usually has a short gate length and a long gate width. With a long gate width, the gate width can be adjusted freely without being restricted by the wiring pitch of bit lines in a direction perpendicular to the wiring direction of bit lines in the sense amplifier layout region, and it becomes possible to provide a sufficient gate width. As to the gate length, the size of a standard gate length itself is a very small length and hence a sufficient adjustment can be made in an adjustment region of a very small length. Also in a direction parallel to the bit line wiring direction in which the adjustment region is restricted due to a layout restriction of adjacent elements in the sense amplifier layout region, it becomes possible to provide such a gate length as ensures a sufficient adjustment region. Both gate width and gate length can be adjusted with a sufficient degree of freedom and it becomes possible to provide a driver-dedicated MOS transistor of a size adjusted appropriately with respect to such characteristics contrary to
Kato Yoshiharu
Kawamoto Satoru
Komura Kazufumi
Arent & Fox PLLC
Fujitsu Limited
Luu Pho M.
Nguyen Van Thu
LandOfFree
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