Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-04-04

2004-05-25

Wille, Douglas (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With pn junction isolation

C257S546000

Reexamination Certificate

active

06740958

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device which has a bipolar transistor and a MISFET (Metal-Insulator-Semiconductor Field Effect Transistor). More particularly, it relates to techniques which are effective when applied to a memory device, such as a DRAM (Dynamic Random Access Memory) device or a SRAM (Static Random Access Memory) device having bipolar transistors, particularly both bipolar transistors and MISFETs.
Even more particularly, it relates to a random access memory with high speed and low consumption of power, where a switching circuit as a complex circuit of a bipolar transistor and metal-oxide semiconductor field effect transistor (hereinafter referred to as “MOSFET”) is adopted as a peripheral circuit (address circuit, timing circuit or the like) of the memory. Moreover, this invention relates to techniques for isolation between elements of the device.
Generally, the present invention is directed to techniques in semiconductor memories, such as Bi-CMOS (bipolar transistor-complementary metal-oxide-semiconductor structure) memories, to avoid destruction of information due to minority carriers.
Semiconductor memories are manufactured as products of large capacity, such as 64K bits, 256K bits, in recent years. Much developmental work has been done on various semiconductor memories, such as dynamic random access memories (DRAMs) and static random access memories (SRAMs).
The so-called one-MOSFET type memory cell, which is composed of one capacitor for storing information charges and one MOS (Metal-Oxide-Semiconductor) FET for switching, has a small occupation area and is suited to raise the density of integration. Therefore, it is extensively adopted as the memory cell of a DRAM.
In the DRAM, circuits other than a memory cell array, namely, peripheral circuits such as various timing generators, an address buffer circuit, an address decoder circuit, data input/output circuits, a sense amplifier and a main amplifier are constructed of CMOS (Complementary MOS) circuits in each of which an N-channel MOSFET and a P-channel MOSFET are combined. Thus, the DRAM is permitted to exhibit a lower power consumption as well as a higher operating speed and to have a higher density of integration. The DRAM which employs the CMOS circuits for the peripheral circuits is described in, for example, “Nikkei Electronics,” Jul. 18, 1983, pp. 188-190.
In order to meet the needs of the age for memories of large capacity, investigations have been made from a viewpoint of manufacturing memories with large capacity, high speed and low consumption of power. Illustratively, in order to attain a still higher operating speed and higher integration density, devices constituting a DRAM need to be made smaller, but the magnitudes of signals to be treated decrease with the smaller devices. In order to treat the small signal magnitude at high speed, a high drivability is required of the constituent device of the circuitry. However, insofar as a CMOS circuit is used as the device, the sizes of MOSFETs cannot be made very large from the viewpoint of the density of integration, and the drivability (conductance g
m
) of each MOSFET is low, so that the operating speed of the memory lowers along with the density of integration. As a result, development of a memory in a mixed state of bipolar transistor and complementary metal-oxide semiconductor field effect transistors (CMOSFET) (the memory being hereinafter referred to as “Bi-CMOS memory”), as shown in Japanese patent application No. 22811/1984 (corresponding to U.S. patent application Ser. No. 701,226), has been considered. Specifically, in order to simultaneously achieve the higher density of integration and the higher operating speed, we have made studies of using a bipolar transistor in the peripheral circuit of the DRAM.
FIG. 29
illustrates a fundamental sectional structure of a BI-CMOS system. Of course, the system shown is merely exemplary. Such Bi-CMOS system is stated in detail in “Nikkei Electronics”, Aug. 12, 1985, pp. 187-208. Shown in the figure are one n-channel MOS (nMOS) transistor, as well as one p-channel MOS (pMOS) transistor, and an n-p-n bipolar (npnBIP) transistor.
Here, letters S, G and D affixed to the nMOS or pMOS indicate the nodes of the source, gate and drain thereof, respectively, while letters C, E and B affixed to the npnBIP transistor, indicate the nodes of the collector, emitter and base thereof, respectively. Besides, in the figure, diffusion layers have only the impurity types thereof written down for the-sake of brevity. Accordingly, as regards portions to which the same symbols are assigned, it is merely indicated that the conductivity types are the same, and the impurity materials and impurity concentrations are selected at will properly according to the purposes of the portions.
The Bi-CMOS memory will now be described briefly.
In an address circuit, a timing circuit or the like as a peripheral circuit within a semiconductor memory, an output transistor for charging and discharging parasitic capacitance in signal lines of long distance, and an output transistor with large fan-out are constituted by bipolar transistors, and a logical circuit for performing logical processing such as inversion, non-inversion, NAND, NOR is constituted by a CMOS circuit. The logical circuit constituted by the CMOS circuit is of low power consumption, and an output signal of the logical circuit is transmitted through the bipolar output transistor with low output impedance to the signal lines of long distance. Since the output signal is transmitted to the signal lines using the bipolar output transistor with low output impedance, dependence of the signal propagation delay time on the parasitic capacitance of the signal lines can be reduced, whereby a semiconductor memory with low consumption power and high speed is obtained.
However, as discussed further below, problems arise in using bipolar transistors in the peripheral circuits of, for example, the DRAM.
Heretofore, in an integrated circuit employing insulated-gate field effect transistors (hereinafter, abbreviated to “MOS transistors”) or bipolar transistors (hereinafter, abbreviated to “BIP transistors”), isolation among the elements of the integrated circuit has been performed by applying reverse bias voltages to p-n junctions. The details are stated in, for example, “Integrated Circuit Technology (1)” (Corona Publishing Co., Ltd.) by Yanai and Nagata, pp. 21-31. In a Bi-CMOS system, a similar device isolation method similar to the above is adopted.
In such a Bi-CMOS system, in the-prior art, the isolation among a large number of devices within a chip is executed by applying the lowest potential in the circuitry to a p-type substrate (p-Sub) and the highest potential in the circuity to the n-type-isolation-layer (nWELL) for forming the pMOS transistor, whereby the junctions of various parts are prevented from falling into the condition of forward bias. That is, with the prior art, in a case where the circuitry operates between a supply voltage (for example, 5 V) and the earth (0 V), the devices are isolated by applying 0 V to the substrate p-Sub and 5 V to the n-type isolation layer. Since, in such a system, the applied voltage to the substrate p-Sub or to the n-type isolation layer is selected at the lowest voltage required for the device isolation, reverse bias voltages to be applied to the p-n junctions can be rendered small, and therefore it is possible to cope with the problems of lowering in-the breakdown voltages of devices, etc. attendant upon the future microminiaturization of the devices.
PROBLEMS FOUND AND ADDRESSED IN THE PRESENT INVENTION
In studying Bi-CMOS memories, the inventors have found various modes for destruction of information in the memory. Thus, the inventors have studied the information destruction modes of the information stored in the memory cell of the Bi-CMOS memory, and have found a novel information destruction mode as hereinafter described and have completed one aspect of the present inventio

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