Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2003-04-18

2004-03-23

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189080

Reexamination Certificate

active

06711088

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to circuit technology for achievement in large-scaling of a memory cell array.
2. Description of the Prior Art
FIG. 17
is a circuit diagram showing an example of a mask ROM configuration of a contact method (contact mask programming method) in accordance with a conventional semiconductor memory device. The mask ROM of the contact method makes it correspond to “0” or “1” of stored data whether a drain of a memory cell transistor is connected to a bit line, or not connected thereto, respectively. In
FIG. 17
, the conventional semiconductor memory device comprises memory cell arrays
1
and
2
, column decoders
3
and
4
, transistors
5
and
6
for precharge, readout circuits
7
and
8
, and an output selection circuit
9
.
The memory cell array
1
is configured so that memory cells M
1
(i, j) (i=1−m, j=1−n) which consist of N-channel MOS transistors may be arranged in a matrix configuration, i.e., forming rows and columns.
Gates of the N-channel MOS transistors which configure each memory cell M
1
(i, j) are connected in common to word lines every n memory cells M
1
(i, j) which have the same numeric value i and are arranged in a row direction. In addition, sources of these N-channel MOS transistors are connected in common to source lines GL
1
i (i=1−m) every n memory cells M
1
(i, j) which have the same numeric value i and are arranged in the row direction. Furthermore, when stored data of the memory cell M
1
(i, j) is “0”, the drain of this N-channel MOS transistor is made to connect to a bit line BL
1
j (j=1−n), and when the stored data of the memory cell M
1
(i, j) is “1”, it is brought to a floating state. In the discussion hereinafter, a gate, a drain, and a source of the each N-channel MOS transistor which configures the memory cell M
1
(i, j) will simply be referred to as the gate, the drain, and the source of the memory cell M
1
(i, j).
In the conventional example, the gates of n memory cells M
1
(i, j) which have the same numeric value i and are arranged in the row direction are connected to word line terminals WLi (i=1−m), respectively, into which row selection signals are inputted. Moreover, the source lines GL
1
i (i=1−m) are connected to a ground terminal having a ground potential.
The memory cell array
2
is configured so that memory cells M
2
(i, j) (i=1−m, j=1−n) which consist of N-channel MOS transistors may be arranged in the matrix configuration, i.e., forming rows and columns.
Gates of the N-channel MOS transistors which configure each memory cell M
2
(i, j) are connected in common to the word lines every n memory cells M
2
(i, j) which have the same numeric value i and are arranged in the row direction. Moreover, sources of these N-channel MOS transistors are connected in common to source lines GL
2
i (i=1−m) every n memory cells M
2
(i, j) which have the same numeric value i and are arranged in the row direction. Furthermore, when stored data in the memory cell M
2
(i, j) is “0”, the drain of this N-channel MOS transistor is made to connect to bit line BL
2
j (j=1−n), and when the stored data in the memory cell M
2
(i, j) is “1”, it is brought to the floating state. In the discussion hereinafter, a gate, a drain, and a source of the each N-channel MOS transistor which configures the memory cell M
2
(i, j) will simply be referred to as the gate, the drain, and the source of the memory cell M
2
(i, j).
In the conventional example, the gates of n memory cells M
2
(i, j) which have the same numeric value i and are arranged in the row direction are connected to the word line terminals WLi (i=1−m), respectively, into which the row selection signals are inputted. Moreover, source lines GL
2
i (i=1−m) are connected to the ground terminal having the ground potential.
The column decoder
3
consists of P-channel MOS transistors Q
1
Pj (j=1−n) and N-channel MOS transistors Q
1
Nj (j=1−n). All sources of the P-channel MOS transistors Q
1
Pj (j=1−n) and drains of N-channel MOS transistors Q
1
Nj (j=1−n) are connected in common. Moreover, gates of the P-channel MOS transistors Q
1
Pj (j=1−n) are connected to column selection signal lines CLPj (j=1−n), respectively, and drains thereof are connected to bit lines BL
1
j (j=1−n), respectively. Moreover, gates of the N-channel MOS transistors Q
1
Nj (j=1−n) are connected to column selection signal lines CLNj (j=1−n), respectively, and sources thereof are connected to bit lines BL
1
j (j=1−n), respectively.
The column decoder
4
consists of P-channel MOS transistors Q
2
Pj (j=1−n) and N-channel MOS transistors Q
2
Nj (j=1−n). All sources of the P-channel MOS transistors Q
2
Pj (j=1−n) and drains of N-channel MOS transistors Q
2
Nj (j=1−n) are connected in common. Moreover, gates of the P-channel MOS transistors Q
2
Pj (j=1−n) are connected to the column selection signal lines CLPj (j=1−n), respectively, and drains thereof are connected to the bit lines BL
2
j (j=1−n), respectively. Moreover, gates of the N-channel MOS transistors Q
2
Nj (j=1−n) are connected to the column selection signal lines CLNj (j=1−n), respectively, and sources thereof are connected to the bit lines BL
2
j (j=1−n), respectively.
The transistor
5
for precharge consists of a P-channel MOS transistor. Then, a gate of the transistor
5
is connected to a precharge control signal line PCLK
1
, a source thereof is connected to a power supply terminal having a power supply potential, and a drain thereof is connected to the sources of the P-channel MOS transistors Q
1
Pj (j=1−n) and the drains of the N-channel MOS transistors Q
1
Nj (j=1−n) which configure the column decoder
3
.
The transistor
6
for precharge consists of a P-channel MOS transistor. Then, a gate of the transistor
6
is connected to a precharge control signal line PCLK
2
, a source thereof is connected to the power supply terminal having the power supply potential, and a drain thereof is connected to the sources of the P-channel MOS transistors Q
2
Pj (j=1−n) and the drains of the N-channel MOS transistors Q
2
Nj (j=1−n) which configure the column decoder
4
.
The readout circuit
7
, whose input is connected to the drain of the transistor
5
for precharge, and the sources of the P-channel MOS transistors Q
1
Pj (j=1−n) and the drains of the N-channel MOS transistors Q
1
Nj (j=1−n) which configure the column decoder
3
, and outputs data to a readout data line SOUT
1
. In the conventional example, assuming that when the stored data in the memory cell M
1
(i, j) is “0”, the readout data line SOUT
1
is brought to a low level, and when the stored data in the memory cell M
1
(i, j) is “1”, the readout data line SOUT
1
is brought to a high level.
The readout circuit
8
, whose input is connected to the drain of the transistor
6
for precharge, and the sources of the P-channel MOS transistors Q
2
Pj (j=1−n) and the drains of the N-channel MOS transistors Q
2
Nj (j=1−n) which configure the column decoder
4
, outputs data to a readout data line SOUT
2
. In the conventional example, assuming that when the stored data in the memory cell M
2
(i, j) is “0”, the readout data line SOUT
2
is brought to the low level, and when the stored data in the memory cell M
2
(i, j) is “1”, the readout data line SOUT
2
is brought to the high level.
The output selection circuit
9
, into which signals of the readout data lines SOUT
1
and SOUT
2
, and a readout data selection line SEL are inputted, outputs data to an output terminal

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