Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2002-09-06
2004-07-06
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185120, C365S185130, C365S189040
Reexamination Certificate
active
06760254
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-272072, filed Sep. 7, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrically erasable and programmable nonvolatile semiconductor memory device (EEPROM), particularly relates to, in the semiconductor memory device having a plurality of banks in which memory elements of a MOS type of transistor structure are formed with the memory elements arranged in a matrix form, the semiconductor memory device having an arrangement in which a certain bank can be read while erase or write is being performed in another bank, and it is utilized for a flash erasable semiconductor memory device (flash memory).
2. Description of the Related Art
A NMOS transistor having double layer stacked gate structure on a double well formed on a semiconductor substrate is known as a memory cell of the EEPROM.
FIG. 4
is a cross-sectional view showing an example of a cell including the NMOS transistor having the double layer stacked gate structure.
In
FIG. 4
, reference numeral
30
is a P type substrate (Psub),
31
is an N type well (Nwell) and
32
is a P type well (Pwell) formed in the N type well. In the N type well
31
, a well leading electrode is formed of an N+type diffusion layer
33
. In the P type well
32
, a source S and a drain D of the NMOS transistor are formed by an N+type diffusion layer
34
and the well leading electrode of the well is formed by a P+ type diffusion layer
35
.
A floating gate FG made of a poly-crystalline silicon layer of a first layer is formed on a gate insulation film
36
, a control gate CG made of the poly-crystalline silicon layer of a second layer is formed with the control gate CG separated by a insulation film
37
.
In the actual semiconductor memory device, a plurality of cells are arranged in a matrix form on one well, any one of cells is selected by a plurality of row lines WL connected to the control gate CG of the cell of each row and a plurality of column lines BL connected to the drain D of the cell of each row. The source S, the N type well
31
and the P type well
32
of all cells are commonly connected with a source line SL.
Operation of the cell will be briefly described as an example of an NOR type memory cell which applies high voltage to the channel to erase.
In-case of erasing data, for example, by applying 10V to the source line SL, the voltage of 10V is applied to the source S, the N type well
31
and the P type well
32
of the cell. By applying, for example, −7V to all row lines WL, the voltage of −7V is applied to all control gates CG. The drain D is made to be a floating state. At this point, electrons in the floating gate FG are emitted into a channel by Fowler-Nordheim (FN) tunneling. A threshold of the cell becomes lower at this state, and data of this erase state is normally referred to as “1”.
In case of writing data, for example, any one of a plurality of row lines WL is set to 9V, for example, any one of a plurality of column lines BL is set to 5V, for example, and the source line SL is set to 0V in order to select the cell to be written. At this point, in the selected cell, electrons are injected into the floating gate FG by hot electron injection. The threshold of the cell becomes higher at this state, and data of this write state is normally referred to as “0”.
In case of reading data, for example, any one of a plurality of row lines WL is set to, for example, 5V, any one of a plurality of column lines BL is set lower voltage (for example, 0.7V) and the source line SL is set to 0V in order to select the cell to be read. At this point, in case that the selected cell is in the write state (data are “0”), current does not flow because the cell is not turned on. On the other hand, in case that data of the selected cell is in the erase state (data are “1”), cell current of about 40 &mgr;A flows because the cell is turned on. The amplitude of the current is sensed and amplified by a sense amplifier circuit (not shown) or the like to read data.
Though the NOR type memory cell which applies high voltage to the channel to erase is taken as the example in the above description of the operation, the same operation is also performed in a memory cell which applies high voltage to the source to erase.
Recently, the semiconductor memory device is used, for example, as a component of a portable device and utilized for storing various programs and personal data, there are strong demands storing programs or data in one semiconductor memory device in order to reduce the number of required memory chips in a system.
However, required time for re-writing data becomes relatively longer in case that the cell shown in
FIG. 4
is used. Normally it takes about 10 &mgr;sec to write data and it takes about several hundreds of msec to as much as several sec for a block to erase data, it is impossible to read data during re-writing the data.
A memory system known as a RWW (Read While Write) type, which is able to read data in a certain memory area while data are written or erased in another memory area, has been proposed.
The present applicant has proposed Japanese Patent Application No. 2000-127106 of “semiconductor device” which can concretely realize a flash memory capable of writing or erasing data and reading data simultaneously by using the NMOS transistor of the double layer stacked gate structure shown in
FIG. 4
as the cell.
FIG. 5
shows an example of concrete arrangement of a part of a flash memory, which is proposed at the moment, capable of writing or erasing data and reading out data simultaneously.
As shown in
FIG. 5
, in a plurality of banks BNK
0
to BNKk, one or a plurality of block circuit groups (in the example, BA
0
to BAi) are arranged in a first direction, the plurality of banks BNK
0
to BNKk are arranged in a second direction perpendicular to the first direction.
In each of the block circuit groups BA
0
to BAi, electrically rewritable memory cells having the MOS structure are arranged in a matrix form respectively, a cell array MA
0
divided by an erase unit, a sub row selection decoder RS
0
, the row line WL, the column line BL, a column selection gate CG
0
and a block decoder BD
0
are provided.
In the banks BNK
0
to BNKk, main row selection decoders RM
0
to RMk, j data line switching circuits DLSW
0
to DLSWk and power supply decoders VD
0
to VDk are provided correspondent to each bank.
In each of the banks BNK
0
to BNKk, main row selection line Mi connected commonly to the block circuit groups BA
0
to BAi in the same bank and j sub data lines SDLj (for example, eight lines or sixteen lines) are also formed.
The sub data lines SDLj on the block circuit groups BA
0
to BAi in the same bank are formed by a first wiring layer in the first direction, connected to j column selection gates CG
0
in each of block circuit groups BA
0
to BAi and connected correspondent to the j data line switching circuits DLSW
0
to DLSWk every bank BNK
0
to BNKk.
The power supply decoders VD
0
to VDk are circuit groups performing power supply control in case of write or erase by a bank unit and decode control for selecting the memory cell.
Out of the bank areas, j main data lines MDL_Rj for read, in which data of the memory cell in a bank selected by read operation (a first operation mode) are read through the j sub data lines and the j data line switching circuits DLSW
0
to DLSWk, are formed by a second wiring layer in the second direction. The j main data lines MDL_Rj for read are connected to j amplifier circuits SA_Rj for read.
Out of the bank areas, j main data lines MDL_Aj for auto, in which data of the memory cell in a bank selected by write or erase operation (a second operation mode) are read through the j sub data lines and the j data line switching circuits DLSWi, are formed by the second wiring layer in the second direction. The j
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