Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-09-21

2003-07-22

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Data security

C365S185080, C365S185290

Reexamination Certificate

active

06597602

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-289314, filed Sep. 22, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a rewritable non-volatile semiconductor memory device using a rewritable non-volatile memory element as in a rewritable memory section for a user for storing data which is inhibited from rewriting such as individual information.
2. Description of the Related Art
In conventional semiconductor memory devices, it may be desirable to inhibit rewriting of some stored data. For example, when copyrighted information such as music is stored in a large capacity semiconductor memory device, individual certification is required for each semiconductor chip to secure the copy right.
For individual certification, it is necessary to output unique data for individual certification written to each semiconductor chip. Thus, different rewrite-inhibited data must be stored in each semiconductor chip with certain means.
The simplest method to achieve the aforementioned object is to make use of the characteristic of nonvolatile memory elements constituting a memory region of a semiconductor memory device being a writable memory such that data is written to a non-volatile memory element formed as in a typical memory region after a wafer process. Such a non-volatile memory element disposed in a memory cell array similar to a typical memory area is preferable for a higher degree of integration since write circuits and read circuits can be shared.
When the non-volatile memory element is rewritable, however, rewriting must be possible before rewrite-inhibited data is stored and a problem occurs in that rewriting is permitted in a rewrite-inhibited memory region through input of an electrical signal unless certain physical changes are added to a semiconductor chip. To address this, conventionally, a circuit as shown in
FIG. 1
has been used to disable alteration of written data after the writing of the data to a rewrite-inhibited region in a memory cell array.
The circuit shown in
FIG. 1
comprises a row decoder
60
for selecting a word line in a rewrite-inhibited region, and a non-volatile data region (memory cell array)
100
including a rewrite-inhibited region comprising nonvolatile memory elements Q
10
, Q
11
and the like. In the conventional circuit shown in
FIG. 1
, the rewrite-inhibited region is disposed in the typical non-volatile data region
100
open to general users. A word line in the rewrite-inhibited region is selected by activating the row decoder
60
different from a typical row decoder selected with an address.
Next, the operation of the row decoder
60
will be described. As described above, the functions required for the rewrite-inhibited region for individual certification are to inhibit data rewriting after data for individual certification is written to each semiconductor chip and to allow reading of the written data for individual certification in a rewrite-inhibited state at the time of individual certification.
In the row decoder
60
shown in
FIG. 1
, a fixed high-level voltage V
0
is input to the gates of N-channel transistors Q
1
, Q
2
, and Q
3
, which would receive address signal in a typical row decoder, to turn on the N-channel transistors Q
1
, Q
2
, and Q
3
. A signal V
0
is an activation signal for the row decoder. The signal &phgr; going high turns on an N-channel transistor Q
4
and turns off a P-channel transistor Q
6
to separate a power supply voltage at high level provided for the source of the P-channel transistor Q
6
.
If a fuse element is connected, a selection signal X at high level for rewrite-inhibited region is input to the gate of an N-channel transistor Q
5
to set the voltage at a node N
1
to low level (ground).
The low-level voltage at the node N
1
is applied as a voltage at high level to the gate of a pass-transistor Q
8
for selecting a word line in the rewrite-inhibited region through a latch circuit including an inverter
13
and a P-channel transistor Q
7
and a voltage conversion circuit
14
to turn on the pass-transistor Q
8
, thereby applying a word line selection voltage to the gates of the non-volatile memory elements Q
10
, Q
11
and the like in the rewrite-inhibited region included in the memory cell array to write data for individual certification. In this case, since an N-channel transistor Q
9
is short-circuited with the fuse element, it is not involved in the operation of the row decoder
60
.
To inhibit rewriting of the data thus written for individual certification, the fuse element formed on the wafer using a metal layer is blown through laser processing. At this point, since a read mode signal is at low level and thus the N-channel transistor Q
9
is off, and the node N
1
is released from the low level, a voltage at low level is applied to the gate of the pass-transistor Q
8
through the inverter
13
of the latch circuit and the voltage conversion circuit
14
to turn off the pass-transistor Q
8
, thereby inhibiting writing of data to the memory elements Q
10
, Q
11
and the like.
When the read mode signal is driven high level with the fuse element blown, the N-channel transistor Q
9
is turned on and the node N
1
goes low. A word line can be selected using the pass-transistor Q
8
to read the data for individual certification written to the non-volatile memory elements Q
10
, Q
11
and the like in the rewrite-inhibited region.
As described above, rewriting has conventionally been inhibited by blowing the fuse element in the row decoder
60
for selection in the rewrite-inhibited memory region. The use of the method, however, requires laser processing for accurately blowing the fuse with laser and takes a long time for a test step after the semiconductor chip fabrication to result in a problem of increased manufacturing cost.
As mentioned above, since a conventional semiconductor memory device capable of individual certification is provided with a rewrite-inhibited function using the blowing of a fuse element, a long time is required for a test step after the semiconductor chip fabrication to cause a problem of increased manufacturing cost.
BRIEF SUMMARY OF THE INVENTION
A semiconductor memory device according to an embodiment of the present invention employs non-volatile memory elements typically constituting a memory cell array to form a rewrite-inhibited region for individual certification instead of a conventionally used fuse element. Before a semiconductor chip is sealed in a package, a voltage at high level is applied to a pad on the semiconductor chip with a probe or the like to set the non-volatile memory elements in the rewrite-inhibited region to a writable state. After data for individual certification is written thereto, the chip is sealed in a package to disable electrical connection to the pad from outside, thereby inhibiting rewriting of the data.
Specifically, a semiconductor memory device according to an embodiment of the preset invention comprises a rewritable non-volatile memory element, an erase circuit configured to erase storage data written to the non-volatile memory element, a circuit configured to write storage data to the non-volatile memory element, a circuit configured to read storage data written to the non-volatile memory element, and a pad formed by opening a passivation film on a surface of a semiconductor chip, wherein erasing and writing of storage data in the non-volatile memory element are allowed by inputting a signal at a first voltage level to the pad, and erasing or writing of storage data in the non-volatile memory element are inhibited by inputting a signal at a second voltage level to the pad.
A semiconductor memory device according to another embodiment of the present invention comprises a memory cell array including non-volatile memory elements. The memory cell array includes a no

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