Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-09-25

2003-07-29

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read only systems

Semiconductive

C365S203000, C365S230060

Reexamination Certificate

active

06600672

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor memory device, and to a circuit technique that ensures high-speed readout even with a miniaturized device at low voltages.
2. Related Background Art
FIG. 9
is a circuit diagram illustrating a configuration of a contact-type mask ROM as a conventional semiconductor memory device. The contact-type mask ROM is configured so that the connection and the disconnection between a drain of a memory cell transistor and a bit line correspond to “1” and “0” as ROM data, respectively.
In
FIG. 9
, the conventional semiconductor memory device is composed of a memory cell array
1
, a row decoder
2
, a precharge transistor
3
, a readout circuit
4
, a bit line selection circuit
14
, and a column decoder
15
.
The memory cell array
1
includes memory cells M(i,j) (i=1 to m, j=1 to n) that are arrayed in matrix of m rows×n columns. Gates of the memory cells M(i,j) are connected with word lines Wi (i=1 to m), respectively. Sources thereof are connected to a ground potential, and drains thereof are connected to bit lines BLj (j=1 to n), respectively, when the memory cell data is “0”, whereas they are floated when the memory cell data is “1”.
The row decoder
2
is supplied with row addresses AR
1
to ARy and a precharge signal PCLK as inputs thereto. The row decoder
2
makes all the word lines Wi (i=1 to m) unselected when the precharge signal PCLK is at a logic “L” level, and it selects the word lines Wi (i=1 to m) corresponding to inputs of the row addresses AR
1
to ARy when the precharge signal PCLK is at a logic “H” level. In this conventional example, the selected word lines Wi have the “H” level, and the other lines Wi have the “L” level.
The precharge transistor
3
is a P-type MOS transistor whose source is connected with a power source potential, whose gate is fed with the precharge signal PCLK, and whose drain is connected to a connection DINA that is connected with the bit line selection circuit
14
.
The readout circuit
4
amplifies a signal at the connection DINA connected with the bit line selection circuit
14
, and outputs memory data to an output terminal DOUT. The output terminal DOUT outputs data of “1” when the connection DINA has the “H” level, and outputs data of “0” when the connection DINA has the “L” level.
The bit line selection circuit
14
is composed of N-type MOS transistors QNj (j=1 to n) whose sources are connected to bit lines BLj (j=1 to n), respectively, whose gates are connected to a bit line selection signal Cj (j=1 to n), respectively, and whose drains are connected to the connection DINA, and P-type MOS transistors QPj (j=1 to n) whose drains are connected to bit lines BLj (j=1 to n), respectively, whose sources are connected to bit line selection signals /Cj (j=1 to n), respectively, and whose sources are connected to a connection DINA connecting the drain of the precharge transistor
3
and the readout circuit
4
.
The column decoder
15
selects bit line selection signals Cj (j=1 to n) and /Cj (j=1 to n) according to each of column addresses AC
1
to ACx supplied thereto. In this conventional example, the selected Cj (j=1 to n) has the “H” level, while the other Cj (j=1 to n) has the “L” level. The selected /Cj (j=1 to n) has the “L” level, while the other /Cj (j=1 to n) has the “H” level.
An operation of reading out data from a memory cell M(i,j) in the semiconductor memory device thus configured is described with reference to a timing chart of
FIG. 10
, taking an operation of reading out data from a memory cell M(
2
,
2
) as an example. In this conventional example, in the initial state, the word lines Wi, the bit line selection signals Cj and /Cj, the bit lines BLj, the connection DINA, and the output terminal DOUT have a ground potential.
In
FIG. 10
, while the precharge signal PCLK is at the “L” level, the row addresses AR
1
to ARy make transition to addresses for selecting the word line W
2
and are inputted to the row decoder
2
, and the column addresses AC
1
to ACx make transition to addresses for selecting the bit line BL
2
and are inputted to the column decoder
15
.
Thus, the row decoder
2
makes all the word lines Wi (i=1 to m) have the “L” level so as to cause the memory cells M(i,j) whose gate are connected with the word lines Wi to be in the non-conducting state. The column decoder
15
causes the bit line selection signals C
2
and /C
2
corresponding to the second column to make transition to the “H” level and the “L” level, respectively, and causes the other bit line selection signals Cj (j=1, 3, . . . n) and /Cj (j=1, 3, . . . n) to make transition to the “L” level and to the “H” level, respectively. This causes only the N-type MOS transistor QN
2
and the P-type MOS transistor QP
2
to make transition to the conducting state, and so as to cause the other N-type MOS transistors QNj (j=1, 3, . . . n) and P-type MOS transistors QPj (j=1, 3, . . . , n) to make transition to the non-conducting state.
Since the precharge signal PCLK is at the “L” level, the precharge transistor
3
is in the conducting state, and the connection DINA that is connected with the bit line selection circuit
14
and the bit line BL
2
connected with the N-type MOS transistor QN
2
and the P-type MOS transistor QP
2
that are in a state of being conducted are charged so as to have a power source potential over a period of time t
0
c.
Subsequently, since the precharge signal PCLK makes transition to the “H” level, the row decoder
2
causes the word line W
2
to make transition to the “H” level, and causes the other word lines Wi (i=1, 3, . . . , m) to remain at the “L” level, so that the memory cells M(
2
,j) (j=1 to n) whose gates are connected with the word line W
2
make transition to the conducting state.
Thereafter, when the memory cell M(
2
,
2
) is not connected with the bit line BL
2
, that is, the ROM data is “1”, charges accumulated in the connection DINA and the bit line BL
2
are not discharged, and the readout circuit
4
outputs data of “1” to the output terminal DOUT. On the other hand, when the memory cell M(
2
,
2
) is connected with the bit line BL
2
, that is, the ROM data is “0”, charges accumulated in the connection DINA and the bit line BL
2
are discharged, so that the readout circuit
4
outputs data of “0” to the output terminal DOUT after a period of time t
0
r.
This conventional semiconductor memory device has the following drawbacks.
Since several hundreds to several thousands of memory cell transistors are connected with a bit line in the semiconductor memory device, there has been a drawback in that it takes a long time to charge a bit line with a large capacity to the power source potential.
Besides, since the bit lines are precharged via the transistors composing the bit line selection circuit
14
, in order to shorten the precharge time, a gate width of the precharge transistor
3
and gate widths of the transistors composing the bit line selection circuit
14
have to be widened so as to lower ON resistances of the transistors of the both.
However, when the gate widths of the transistors composing the bit line selection circuit
14
are widened, gate capacitances thereof increase, thereby causing load capacitances of bit line selection signals supplied to the gates to increase. This results in an increase in the load capacitances charged by the precharge transistor
3
, thereby causing the time required for the bit line selection to be prolonged.
Besides, since the gate width of the memory cell transistor is reduced to be as small as possible with a view to decreasing the space occupied by the memory cell transistor, there also has been a drawback in that the ON resistance becomes high and that a time required for discharging charges accumulated up to the power source potential becomes long.
Furthermore, in the case where i

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