Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-04-17

2003-06-10

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230090

Reexamination Certificate

active

06577553

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, particularly, to an SRAM alternative memory replaceable with a static random access memory (SRAM), having compatibility with an SRAM. More particularly, the invention relates to the configuration for setting an SRAM alternative memory into a specific mode.
2. Description of the Background Art
In an application of portable equipment, an SRAM is used as an internal memory because of its high processing speed. A memory cell of the SRAM is constructed of four transistors and two load elements, and the occupying area of the SRAM cell is large. Therefore, it is difficult to implement a memory of a large storage capacity in a limited area.
As the functions of portable equipment are enhanced, it is necessary to process image data and audio data. The amount of data to be processed becomes enormous and a memory of a large storage capacity is required as a memory device for the portable equipment. When using an SRAM as the internal memory, it is difficult to implement the memory of a large storage capacity in a small occupying area, so that a requirement of down-sizing and lightening high-function portable equipment cannot be met.
On the other hand, the memory cell of a dynamic random access memory (DRAM) is constructed of one transistor and one capacitor in general. The DRAM has, therefore, an advantage that the occupying area of the memory cell is smaller than that of the SRAM. The DRAM is suitable for constructing a memory of a large storage capacity in a small occupying area. However, the DRAM stores data in the capacitor and the stored data is lost by a leak current, so that refreshing operation for holding stored data has to be periodically performed. During execution of the refreshing, an external device such as a processor cannot access the DRAM and is kept in a wait state, so that the processing efficiency of the system is lowered.
The DRAM is designated of a sleep mode and held in a standby state in a waiting time in portable equipment or the like. Also in the sleep mode, however, stored data has to be held and has to be periodically refreshed. Therefore, an ultra low standby current condition of the order of &mgr;A in the sleep mode required in a specification or the like cannot be satisfied.
In order to implement the memory of a large storage capacity with a small occupying area, a DRAM-based memory has to be used. In the case of using such a DRAM-based memory (hereinbelow, called an SRAM alternative memory), the memory has to be replaced without significantly changing the conventional system configuration. That is, compatibility of pins is required. Here, the “memory” indicates a memory device connected to a device such as an external processor via pin terminals.
Different from a synchronous memory operating synchronously with a clock signal such as a system clock, an SRAM operates statically according to an external control signal. In order to prevent the load of the external processor from increasing, the SRAM alternative memory is required to operate under the same operating conditions (signal timings) as those of the SRAM.
Particularly, in the case of designating various operation modes in the SRAM alternative memory, in view of compatibility of pins, the operation modes have to be set by using signals prepared for a conventional SRAM. Particularly, as for designation of an operation mode which is not prepared for the conventional SRAM, signals used in the SRAM are generally a chip enable signal CE, an output enable signal OE, and a write enable signal WE, and therefore, a complicated signal timing relation cannot be used for setting a specific operation mode. In the case of designating a specific operation mode with a relation of the timings of signals different from the timings of signals used in a general SRAM, an external device such as a memory controller has to be provided with a new function. Consequently, compatibility with a conventional SRAM cannot be maintained, and a load on the external device increases.
SUMMARY OF THE INVENTION
An object of the invention is to provide an SRAM alternative memory having pin compatibility with an SRAM.
Another object of the invention is to provide a semiconductor memory device capable of designating an internal operation mode by using signals similar to those used for an SRAM.
Still another object of the invention is to provide a semiconductor memory device capable of designating a specific operation mode asynchronously with a clock signal without increasing the number of pin terminals.
Further object of the invention is to provide a semiconductor memory device having a circuit for setting a command entry mode for designating a specific operation mode by using an interface compatible with an SRAM.
A semiconductor memory device according to a first aspect of the present invention includes: mode detecting circuitry for detecting that external signals of a predetermined set are applied in a combination of specific logic states a predetermined number of times successively; and mode setting circuitry for setting a specific mode in response to a detection signal from the mode detecting circuitry.
A semiconductor memory device according to a second aspect of the invention is a semiconductor memory device accessed in accordance with an external signal in a normal operation mode, and includes a command decoder that is made active in a specific mode to decode a plurality of predetermined external signals out of the external signals for generating a signal for setting an internal state to a predetermined state. The command decoder generates a signal for designating an operation related to a standby state.
A semiconductor memory device according to a third aspect of the present invention is a semiconductor memory device accessed in accordance with an external signal in a normal operation mode, and includes mode detecting circuitry for detecting that a predetermined set of external signals out of the external signals is applied in a combination of specific logic states a predetermined number of times successively; mode setting circuitry for setting a specific mode in response to a detection signal of the mode detecting circuitry; and a command decoder that is made active in accordance with an output signal of the mode setting circuitry to decode a plurality of predetermined external signals out of the external signals for generating a signal for setting an internal status to a predetermined status. The command decoder generates a signal for designating an operation related to a standby state.
By setting the internal state in accordance with the states of predetermined external signals, the internal state can be set into a desired state by using signals of a conventional SRAM. Thus, a semiconductor memory device having compatibility with a convention SRAM can be implemented.
By the construction that the semiconductor memory device enters a specific mode when a specific state is executed a predetermined number of times successively, the semiconductor memory device can be prevented from entering the specific mode erroneously in the normal mode. Thus, a stably operating semiconductor memory device can be implemented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5905690 (1999-05-01), Sakurai et al.
patent: 5970021 (1999-10-01), Sakurai
patent: 6201748 (2001-03-01), Nakamura et al.

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