Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-12-27

2003-09-02

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189110

Reexamination Certificate

active

06614712

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to a semiconductor memory device equipped with an isolation signal generating circuit for controlling electrical isolation between a cell array and a sense amplifier. The present invention is also concerned with a semiconductor memory device of a hierarchical arrangement of word drivers for driving word lines.
2. Description of the Related Art
First, a first conventional semiconductor memory device will be described with reference to
FIGS. 1 and 2
.
FIG. 1
is a circuit diagram of a part of a DRAM (Dynamic Random Access Memory), which is the first conventional semiconductor memory device. The DRAM shown in
FIG. 1
employs a shared sense amplifier formation in which a sense amplifier is shared by neighboring cell arrays. The DRAM also employs a hierarchical arrangement of word drivers so that each word driver includes a main word driver and a sub word driver.
The DRAM includes cell arrays
1
-
9
, main word drivers
10
-
12
, and sub word drivers
13
-
24
. The main word drivers
10
-
12
drive main word lines. The sub word drivers receive output signals of the main word drivers
10
-
12
and sub word selection signals that are output by a sub word selection signal generating circuit (not illustrated for the sake of simplicity), and select involved memory cells.
Column decoders
25
-
27
decode a column address signal and select columns based on decoding. Sense amplifier parts
28
-
39
are shared by neighboring cell arrays in a wiring direction of bit lines, and include a sense amplifier and a bit line precharge circuit.
The DRAM includes row block selecting signal lines
40
-
45
, and a timing signal line
46
. The DRAM includes isolation signal generating circuits
47
-
52
, which receive the row block selecting signals and a timing signal, and thus generate isolation signals for controlling electrical connection/disconnection between the neighboring cell arrays and the sense amplifier parts in the direction in which the bit lines run.
The DRAM includes isolation signal lines
53
-
58
, and isolation circuits
59
-
76
. The isolation signal lines
53
-
58
carry isolation signals respectively output by the isolation signal generating circuits
47
-
52
. The isolation circuits
59
-
76
respectively have, as switching elements, isolation transistors, which are turned ON/OFF by the isolation signals in order to control electrical connection and disconnection between the cell arrays and sense amplifiers which are adjacent in the direction in which the bit lines run.
In the DRAM thus configured, a read/write operation enables the cell arrays connected to selected main word lines, sub word drivers and sense amplifier parts associated with the selected main word lines. Further, the isolation transistors of the isolation circuits involved in the above read/write operation.
FIG. 2
is a circuit diagram illustrating an isolation operation performed in the DRAM that is described as the first conventional semiconductor memory device in the present specification. For example, when the word lines driven by the main word driver
11
are selected, the cell arrays
4
-
6
, the sub word drivers
17
-
20
, and the sense amplifier parts
31
-
36
are enabled within the circuit part shown in
FIG. 2
, while the isolation transistors of the isolation circuits
62
-
64
and
71
-
73
are turned OFF. The isolation transistors of the isolation circuits
59
-
61
,
65
-
70
, and
74
-
76
are maintained in the ON state.
Thus, electrical connections are made between the cell array
4
and the sense amplifier parts
31
and
34
, between the cell array
5
and the sense amplifier parts
32
and
35
, and between the cell array
6
and the sense amplifier parts
33
and
36
. In contrast, the cell arrays
1
,
2
,
3
,
7
,
8
and
9
are respectively disconnected from the sense amplifier parts
31
,
32
,
33
,
34
,
35
and
36
.
A description will be given, with reference to
FIGS. 3 through 5
, of a second conventional DRAM, which employs the shared amplifier formation. The DRAM also employs a hierarchical arrangement of word drivers so that each word driver includes a main word driver and a sub word driver. Further, each isolation signal generating circuit is hierarchically arranged so as to include a main isolation signal generating circuit and a sub isolation signal generating circuit.
Referring to
FIG. 3
, the second conventional DRAM includes row block selection signal lines
77
-
82
, a timing signal line
83
, main isolation signal generating circuits
84
-
89
, and main isolation signal lines
90
-
95
. The main isolation signal generating circuits
84
-
89
receive the row block selection signal lines
77
-
82
and a timing signal carried over the timing signal line
83
, and generate resultant main isolation signals, which are transferred over the main isolation signal lines
90
-
95
.
The second conventional DRAM includes column block selection signal lines
96
-
101
, sub isolation signal generating circuits
102
-
137
, and sub isolation signal lines
138
-
155
. The sub isolation signal generating circuits
102
-
137
receive the main isolation signals and column block selection signals carried over the column block selection signal lines
96
-
101
, and generate resultant sub isolation signals, which are transferred over the sub isolation signal lines
138
-
155
.
The second conventional DRAM includes sub word drivers
156
-
173
, and has the same cell arrays
1
-
9
, main word drivers
10
-
12
, column decoders
25
-
27
, the sense amplifier parts
28
-
39
, and isolation circuits
59
-
76
as those of the first conventional DRAM.
In the second conventional DRAM, a read/write operation enables the cell arrays connected to selected main word lines, sub word drivers and sense amplifier parts associated with the selected main word lines. Further, the isolation transistors of the isolation circuits involved in the above read/write operation.
FIG. 4
is a circuit diagram illustrating an isolation operation performed in the second conventional. For example, when memory cells in the cell array
5
are selected, the cell array
5
, the sub word drivers
164
and
165
, the sub isolation signal generating circuits
110
,
111
,
128
and
129
, and the sense amplifier parts
32
and
35
are enabled within the circuit part shown in FIG.
4
.
Thus, the isolation transistors of the isolation circuits
63
and
72
are turned OFF, while those of the isolation circuits
59
-
62
,
64
-
71
, and
73
-
76
are maintained in the ON state. Thus, connections of the cell array
5
with the sense amplifier parts
32
and
35
are made, while the cell arrays
2
and
8
are disconnected from the sense amplifier parts
32
and
35
, respectively.
FIG. 5
is a circuit diagram of a configuration of the main isolation signal generating circuits and the sub isolation signal generating circuits employed in the second conventional DRAM. A main isolation signal generating circuit
174
includes a NAND circuit
175
, an inverter
176
, PMOS (P-channel Metal Oxide Semiconductor) transistors
177
-
179
, and NMOS (N-channel MOS) transistors
180
-
182
.
A sub isolation signal generating circuit
183
includes PMOS transistors
184
-
187
, and NMOS transistors
188
-
191
. A symbol VPP denotes a boosted voltage obtained by boosting a power supply voltage supplied from the outside of the DRAM. A symbol VSS denotes a ground potential.
A description will be given, with reference to
FIGS. 6 through 8
, of a third conventional DRAM.
FIG. 6
illustrates a layout of a core part of the third conventional DRAM, which employs the shared sense amplifier formation and the hierarchical arrangements of the word drivers and isolation signal generating circuits. Further, the third conventional DRAM includes a hierarchical arrangement of sub word selection signal generating circuits (¼ signal generating circuits) so that each of the circuits is made up of a main sub-word

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