Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-09-17

2002-10-22

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

C257S208000, C257S211000, C257S202000, C257S401000, C257S390000, C257S903000

Reexamination Certificate

active

06469328

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device such as a static random access memory (SRAM).
In semiconductor memory devices, memory cells occupy a large portion of the device area. Hence, the memory cell is an important factor which determines the size, access speed and power consumption of the semiconductor memory device.
2. Description of the Related Art
First, a description will be given of a memory cell of a conventional 1-read-write/1-read (1RW/1R) RAM.
FIG. 1
is a circuit diagram showing a memory cell of a conventional 1RW/1R RAM.
FIG. 2
is a diagram showing a layout of the memory cell of the conventional 1RW/1R RAM.
FIG. 3
is a diagram for explaining various symbols used to indicate a gate polysilicon layer, a gate contact layer, a source/drain contact region, a source/drain region, a well contact region, a cell frame, a P-type well region, and an N-type well region in the layout shown in FIG.
2
.
In
FIG. 1
, P-channel MOS transistors Trp
1
and Trp
2
, N-channel MOS transistors Trn
1
through Trn
8
, bit lines BLA, BLB, XBLA and XBLB, word lines WLA and WLB, and power lines VDD and VSS for respectively supplying power supply voltages VDD and VSS are coupled as shown.
In
FIG. 2
, gates of the transistors Trn
3
and Trn
4
are connected by a gate polysilicon layer
61
, and gates of the transistors Trn
5
and Trn
7
are connected by a gate polysilicon layer
62
. This is because the gates of the transistors Trn
3
and Trn
4
are connected to the same word line WLA, and the gates of the transistors Trn
5
and Trn
7
are connected to the same word line WLB, as may be seen from FIG.
1
.
When the layout shown in
FIG. 2
is employed, portions where the transistors are formed are inevitably separated and a large area is occupied thereby. That is, even among the N-channel MOS transistors which are of the same nMOS type, the source/drain regions are separated and an additional area is occupied thereby. More particularly, the cell frame shown in
FIG. 2
is separated into the regions of the transistors Trn
1
and Trn
3
, the transistors Trn
2
and Trn
4
, the transistors Trn
5
and Trn
6
, and the transistors Trn
7
and Trn
8
.
On the other hand, since the gate polysilicon layer
61
of the transistors Trn
3
and Trn
4
cannot be arranged in the same direction as gate polysilicon layers
63
and
64
of the other transistors, the 1RW/1R RAM is easily affected by inconsistencies introduced during the production process of the memory cell. In other words, the dimensional accuracies of the gate polysilicon layers
61
and
62
and the gate polysilicon layers
63
and
64
which extend in different directions become different due to the inconsistencies introduced during the production process. For this reason, even if the gate polysilicon layers
61
and
62
are designed to have the same length as the gate polysilicon layers
63
and
64
, for example, the actual resistances of the gate polysilicon layers
61
and
62
become different from the actual resistances of the gate polysilicon layers
63
and
64
. As a result, the access speed and the power consumption of the memory cell are affected by the different resistances, and the balance of the memory cell as a whole deteriorates. Therefore, it is difficult to guarantee a stable operation of the semiconductor memory device.
As described above, in the conventional semiconductor memory device, there were problems in that it is difficult to reduce the area occupied by the memory cell, and that it is difficult to guarantee a stable operation of the semiconductor memory device due to the effects of the inconsistencies introduced during the production process.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor memory device in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide a semiconductor memory device which can reduce an area occupied by a memory cell and can guarantee a stable operation of the semiconductor memory device by minimizing effects caused by inconsistencies which are introduced during a production process of the semiconductor memory device.
Still another object of the present invention is to provide a semiconductor memory device comprising a memory cell formed by a plurality of transistors, wherein each of gate wiring layers of all of the transistors forming the memory cell is arranged to extend in one direction. According to the semiconductor memory device of the present invention, it is possible to reduce an area occupied by the memory cell, and to guarantee a stable operation of the semiconductor memory device by taking measures so as to be less affected by inconsistencies introduced during a production process of the semiconductor memory device.
Of the transistors forming the memory cell, first transistors which are coupled to word lines may be arranged on an outer side of second transistors which are coupled to a power supply, within the semiconductor memory device. In addition, of the second transistors, a source/drain of a second transistor coupled to the power supply and a substrate contact of the power supply may be used in common. Furthermore, of the second transistors, a source/drain of a second transistor coupled to another power supply which is different from the power supply and a substrate contact of the other power supply may be used in common. According to the semiconductor memory device of the present invention, it is possible to effectively reduce the area occupied by the memory cell by the transistor arrangement and the common use of the contact.
The first transistors and the second transistors which are coupled to the power supply are made of N-channel MOS transistors, and the second transistor which is coupled to the other power supply may be made of a P-channel MOS transistor.
The semiconductor memory device may further comprise signal lines including word lines, and a power line, where the power line is arranged between the signal lines in a single wiring layer. According to the semiconductor memory device of the present invention, it is possible to reduce the coupling capacitance introduced between the signal lines, and prevent generation of noise and inversion (transformation) of data.
A plurality of memory cells may be arranged in an array, an adjacent memory cell may be arranged adjacent to a certain memory cell, and a source/drain of the transistors forming the adjacent memory cell and a bulk layer of a substrate contact may be used in common by reversing a layout of the certain cell with respect to both an x-axis direction and a y-axis direction. In addition, the semiconductor memory device may further comprise power lines, and signal lines, where a plurality of memory cells are arranged in an array, an adjacent memory cell is arranged adjacent to a certain memory cell, and the power lines and the signal lines with respect to the adjacent memory cell are used in common with the certain memory cell by reversing a layout of the certain memory cell with respect to both an x-axis direction and a y-axis direction. According to the semiconductor memory device of the present invention, it is possible to effectively reduce the area occupied by the memory cell array.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.


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