Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-12-21

2002-12-24

Elms, Richard (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S189050, C365S189120

Reexamination Certificate

active

06498741

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and more specifically to the circuit arrangement of a semiconductor memory device operations of which are synchronized with a high-frequency clock signal. This application is based on Japanese Patent Application No. 10-364613, filed Dec. 22, 1998, the content of which is incorporated herein by reference.
Such a semiconductor memory device as is synchronized with a high-frequency clock signal is referred hereinafter to as a synchronous memory. The circuit arrangement of a conventional synchronous memory
100
is shown in FIG.
1
. The memory
100
is roughly divided into a memory core section
101
and an I/F circuit section.
The I/F circuit section includes right and left shift register sections
102
adjacent to the memory core section
101
, right and left input/output (I/O) circuits
106
corresponding to the right and left shift register sections, a delayed locked loop (DLL) circuit
111
, and a control logic circuit
112
.
The DLL circuit
111
produces an internal write data control clock signal rclk in synchronization with an externally applied write clock signal RXCLK and an internal read data control clock signal tclk in synchronization with an externally applied read clock signal TXCLK.
The control logic circuit
112
performs logical operations on a protocol entered through an external command signal COMMAND to produce control signals for the memory.
The right and left I/O circuits
106
are responsive to the internal write data control signal rclk to take in serial write data DQ<
0
:
7
> and DQ<
8
:
15
>, respectively, from external I/O data lines and then output internal serial write data eWrite and oWrite to the shift register sections
102
each consisting of plural shift registers.
Further, the right and left I/O circuits are responsive to the internal read data control signal tclk to take in internal serial read data eRead and oRead from the left and right shift register sections, respectively, and then output serial read data DQ<
0
:
7
> and DQ<
8
:
15
>, respectively, onto the external I/O data lines.
Here, <
0
:
7
> and <
8
:
15
> represent the low-order eight bits and the high-order eight bits, respectively, of 16-bit data. The letters e and o affixed to Read and Write represent even-numbered and odd-numbered bits of data, respectively.
The shift register sections
102
are each responsive to a control signal to take in internal parallel read data RD<
0
:
7
> output from the memory core section
101
in a read operation and to write internal parallel write data WD<
0
:
7
> output therefrom into the memory core section in a write operation.
Thus, the right and left shift registers
102
convert internal parallel read data RD<
0
:
7
> read from the memory core section
101
into internal serial read data eRead and oRead at read time and convert internal serial write data eWrite and oWrite from the I/O circuits
106
into internal parallel write data WD<
0
:
7
> at write time.
The memory core section
101
includes, as in a normal DRAM circuit, a memory cell array, a sense amplifier, a row decoder, a column decoder, a redundancy fuse, and a DQ buffer.
In
FIG. 2
, there is illustrated, in the layout of the conventional synchronous memory, the flow of data from the memory core section
101
to the I/O circuits
106
with conversion from parallel form to serial form by the shift register sections
102
. Here, the right and left I/O circuits
106
included in a peripheral circuit section
105
enclosed with dashed lines are consecutively numbered
0
through
7
and
8
through
15
.
In writing into the memory core section
101
, serial write data from the I/O circuits
106
are entered into the shift register sections
102
for conversion into parallel write data and the resulting parallel write data are written into the memory core section
101
.
Thus, the flow of data in a write operation is the reverse of that in a read operation. In
FIG. 2
, therefore, there is illustrated the flow of data in a read operation by way of example.
In
FIG. 2
, four memory core sections
101
are placed above and below the peripheral circuit section
105
. The left-hand memory core sections
101
are each allocated areas for eight bits in correspondence with the left-hand 8-bit I/O circuit
106
assigned consecutive numbers
0
through
7
. Likewise, the right-hand memory core sections
101
are each allocated areas for eight bits in correspondence with the right-hand 8-bit I/O circuit
106
assigned consecutive numbers
8
through
15
. As a result, a 16-bit synchronous memory is constituted as a whole.
In this manner, the cell array is allocated areas from (I/O)
0
<
0
:
7
> to (I/O)
15
<
0
:
7
> each of eight bits as shown in FIG.
2
. If the synchronous memory is active, then either upper left and lower right memory core sections or lower left and upper right ones will be selected in combination by an address signal.
Data read from each memory core section in a parallel form, eight bits at a time, is converted to 8-bit serial data in the corresponding shift register section
102
. The shift register section
102
is illustrated in detail in
FIGS. 3A and 3B
.
FIG. 3A
shows the shift register section
102
in enlarged form. The shift register section
102
has shift registers
102
a
each corresponding to a respective one of the I/O circuits (I/O)
0
through (I/O)
7
. Odd-numbered bits of data and even-numbered bits of data (hereinafter referred simply as to even and odd data) are shifted in the shift register section in synchronization with rising and falling edges, respectively, of the internal read data control clock tclk.
That is, eight-bit parallel read data of RD
0
<
0
:
7
> to RD
7
<
0
:
7
> read from the memory core section are entered into the shift registers
102
a
and odd serial read data of oRead
0
to oRead
7
and even serial read data of eRead
0
to eRead
7
are read from the shift registers
102
a.
Odd serial write data of oWrite
0
to oWrite
7
and even serial write data of eWrite
0
to eWrite
7
are entered into the shift registers
102
a
and 8-bit parallel write data of WD
0
<
0
:
7
> to WD
7
<
0
:
7
> are output from the shift registers.
FIG. 3B
shows the circuit arrangement of the shift register
102
a
, which includes a read register
107
and a write register
108
.
The read register
107
includes first and second shift registers. The first shift register includes four cascade-connected flip-flops (FFs)
109
that receive odd parallel read data RD<
1
>, RD<
3
>, RD<
5
>, and RD<
7
> and output serial read data oRead. The second shift register includes four cascade-connected FFs
110
that receive even parallel read data RD<
0
>, RD<
2
>, RD<
4
>, and RD<
6
> and output serial read data eRead.
Likewise, the write register
108
includes first and second shift registers. The first shift register includes four cascade-connected FFs
109
that receive odd serial write data owrite and output odd parallel write data WD<
1
>, WD<
3
>, WD<
5
> and WD<
7
>. The second shift register includes four cascade-connected FFs
110
that receive even serial write data eWrite and output even parallel write data WD<
0
>, WD<
2
>, WD<
4
> and WD<
6
>.
Thus, the read register
107
and the write register
108
provide parallel-to-serial conversion and serial-to-parallel conversion, respectively.
Next, reference will be made to timing diagrams of
FIGS. 4 through 7
to describe read and write operations of the synchronous memory in terms of one memory core section
101
and its associated shift register section
102
and I/O circuit
106
.
First, an example of a read operation will be described with reference to FIG.
4
. Eight-bit parallel read data RD<
0
:
7
> is output from a memory core section
101
at a fixed time after the entry of a read command signal COMMAND.
The odd bits
1

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