Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-05-29

2002-02-26

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S194000

Reexamination Certificate

active

06351431

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as a random access memory (hereinbelow referred to as a RAM), and in particular, to a technique for initializing the data values stored in a RAM.
2. Description of the Related Art
The data values held in cache memories and in RAMs that are widely used are generally undefined when the supply of power is started. Therefore, it is often necessary to initialize every data value held in a RAM (e.g., to set the data value stored in every memory cell to “0”) during the period starting immediately after a start of the supply of power and ending when the use of the RAM begins.
There are two ways of carrying out the initialization of the data values stored in a RAM, namely, a technique by means of software and a technique by means of hardware.
According to the general software technique, after the supply of power has been started and a computer has started its operation, an initialization program is started to initialize the data values stored in the RAM by writing “0” into every memory cell (every address). In general, at least one clock cycle is required for initializing the data value stored in a single memory cell, so that at least a time, measured in clock cycles, equal to the number of memory cells is required for initializing the data values stored in every memory cell.
On the other hand, a first example of the hardware technique is disclosed in Japanese Unexamined Patent Application, First Publication No. Hei 11-134865. According to this technique, as shown in
FIG. 3
, in addition to the same structure of a normal SRAM (Static RAM) comprising two inverters
108
and
109
and two switching transistors
110
and
111
, an initialization transistor
202
, to which a reset signal is supplied, is provided in each memory cell
201
A,
201
B, . . . ,
201
H. An initialization signal RESET is commonly supplied to the gate electrode of every initialization transistor
202
. When the initialization signal RESET is set to an activation level upon the start of the supply of power, all of the initialization transistors
202
provided in the
10
memory cells
201
A to
202
H conduct so as to set the input of the inverter
109
to “0”, whereby the data value held in a latch circuit comprised by the inverters
108
and
109
is initialized. As described above, according to the first example, the data values held in all the memory cells are simultaneously initialized.
A second example of the hardware technique is disclosed in Japanese Unexamined Patent Application, First Publication No. Sho 61-214198. According to this technique, a counter/decoder
115
, which comprises a counter and a decoder controlled by the output from the counter, is provided as shown in FIG.
4
. When the data values stored in a RAM are initialized, the value of the counter is incremented to sequentially activate one of a plurality of word lines, and “0”s are simultaneously written into a plurality of memory cells that are connected to an activated word line.
However, according to the software initialization technique described above, a time, measured in clock cycles, equal to the number of memory cells is required for initializing the data values stored in the RAM. It is therefore difficult to initialize all of the data values stored in the memory cells in a shorter time.
On the one hand, the hardware technique according to the first example requires seven transistors for individual memory cells
201
A to
201
H as shown in FIG.
3
. More specifically, since each inverter
108
and
109
comprises two transistors, seven transistors are required for forming a memory cell, which comprises the switching transistors
110
and
111
, the initialization transistor
202
, and the two inverters. Furthermore, according to the first example, wires for supplying the initialization signal RESET to the initialization transistor
202
provided in the individual memory cells should be provided within the area of the individual memory cells. In view of the above, with the first example, the area required for constructing the memory cells increases, resulting in a problem in that the area of the chip increases.
On the other hand, the second example requires a clock (not shown in the figures) for working the counter provided in the counter/decoder
115
. In addition, the size of the circuit for constructing the counter/decoder
115
is considerably large. Therefore, a problem arises in that the chip area increases as does in the first example.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor memory device that is capable of initializing the data values stored in the memory cells in a shorter time without increasing the size of a chip.
A semiconductor memory device of the present invention is provided with a plurality of word lines; a plurality of data lines; a plurality of memory cells which are arranged at the intersection of the word lines and the data lines; a level setting circuit which sets the levels of the data lines to a predetermined initialization level when an initialization signal, which is activated when the data values stored in the memory cells are initialized, is activated; a delay circuit which delays the initialization signal to generate a plurality of delayed initialization signals, each of which corresponds to one of the word lines, and the delay times thereof differ from each other; and a logic circuit which sets the level of one of the word lines corresponding to one of the delayed initialization signals to an activation level when the corresponding delayed initialization signal is activated.
In this way, the present invention comprises the delay circuit for successively delaying the initialization signal, and the memory cells connected to an activated word line are set to a predetermined initialization level, while successively activating the word lines with the delayed initialization signals supplied from the delay circuit. Therefore, it is possible to initialize all of the memory cells asynchronously with a clock in a shorter time in comparison with the software initialization technique. Further, in the present invention, since a plurality of word lines are not simultaneously activated, it is not necessary to simultaneously carry out the writing of data into a plurality of memory cells connected to the same data line. Therefore, the driving power for carrying out the writing of data into a single memory cell is sufficient for the driving power of elements constituting the level setting circuit such as transistors, and thus the area can be reduced.
Unlike the conventional hardware technique according to the first example, it is not necessary for the present invention to provide initialization transistors as well as wires for supplying initialization signals thereto in the area of the memory cells, and hence the area can be reduced in comparison with the first example.
In addition, unlike the conventional hardware technique according to the second example, the present invention does not require complicated circuits such as a counter. The present invention can be comprised, for example, of a delay circuit comprising inverters connected in series, and a logic circuit comprising OR gates and the like. It is therefore not necessary for the present invention to provide complicated circuits such as a counter as well as a clock signal for operating the counter, thereby enabling a simple circuit structure.


REFERENCES:
patent: 4984215 (1991-01-01), Ushida
patent: 11-288587 (1999-10-01), None

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