Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-01-17

2002-10-08

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230060

Reexamination Certificate

active

06463005

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor memory devices, and more particularly to synchronous semiconductor memory devices having access to a memory cell array based on an n-bit prefetch mode.
BACKGROUND OF THE INVENTION
In a synchronous semiconductor memory device it is desirable to operate the device at a high external clock frequency. As a result, the synchronous memory device may have to be capabile of being read from and written to at high speeds. One method of increasing the speed in accessing a synchronous memory device is by using an n-bit prefetch (n is an integer greater than 1) whereby n-bits of data are accessed from the memory array at a first portion of a read operation and then synchronously output from the synchronous memory device on subsequent clock cycles. Examples of a 2-bit prefetch operation in a synchronous semiconductor memory device are disclosed in Japanese Patent Application Laid-Open No. Hei 9-63263 (Semiconductor Memory Device) and Japanese Patent Application Laid-Open No. Hei 11-39871 (Synchronous Type Semiconductor Memory Device).
One such example of a synchronous semiconductor memory device is a Synchronous Dynamic Random Access Memory (SDRAM). To better understand the various aspects of the present invention a conventional 2-bit prefetch operation will be described with respect to a SDRAM. Referring now to
FIG. 15
, a SDRAM with a conventional 2-bit prefetch operation is set forth. The SDRAM of
FIG. 15
includes a Y-address buffer decoder
100
, a memory cell array
200
, and sense amplifiers (
301
(AMP
1
) and
302
(AMP
2
)). The memory cell array
200
is divided into memory cell segments (
201
and
202
) with each memory cell segment (
201
and
202
) being equal halves of the memory cell array
200
.
The Y-address buffer
100
receives a Y-address (column address) signal and an external master clock signal (CLK) from outside the chip or integrated circuit. Based on the value of the Y-address signal, the Y-address buffer decoder
100
activates a column switch line from a group of column switch lines YSW
1
corresponding to the memory cell segment
201
and a column switch line from a group of column switch lines YSW
2
corresponding to the memory cell segment
202
. The column switch line is activated synchronously with the clock signal CLK.
The column switch lines YSW
1
and YSW
2
designate even column switch lines (YSW
1
) and odd column switch lines (YSW
2
). Thus, when the Y-address buffer decoder
100
receives an even Y-address value (Y), the Y-address buffer decoder
100
activates a column switch line, which corresponds to the Y-address value (Y), from the group of column switch lines YSW
1
. Also, at the same time, the Y-address buffer decoder
100
activates a column switch line, which corresponds to the Y address value (Y+1), from the group of column switch lines YSW
2
.
However, when the Y-address buffer decoder
100
receives an odd Y-address value (Y), the Y-address buffer decoder
100
activates a column switch line, which corresponds to the Y-address value (Y), from the group of column switch lines YSW
2
. Also, at the same time, the Y-address buffer decoder
100
activates a column switch line, which corresponds to the Y address value (Y+1), from the group of column switch lines YSW
1
.
Thus, a memory cell from both memory cell segments (
201
and
202
) can be simultaneously accessed constituting a 2-bit prefetch. The 2 prefetched bits correspond to bits with consecutive column addresses. The memory cell array
200
is divided into two equal halves where each half corresponds to a memory cell segment (
201
or
202
). Memory cell segment
201
contains only memory cells that have even column addresses and memory cell segment
202
contains only memory cells that have odd column addresses.
Additionally, an X-address (row address) buffer decoder (not shown) is coupled to the memory cell segments (
201
and
202
) to activate a row of memory cells in each memory cell segment (
201
and
202
). For example, a X-address signal is received externally from the SDRAM and used to activate a word line (not shown) in each memory cell segment (
201
and
202
). Then, based on the Y-address signal (column address) received externally from the SDRAM, a column switch line is selected from each of the groups of column switch lines (YSW
1
and YSW
2
) to access a bit with an even column address from memory cell segment
201
and a bit with an odd column address from memory cell segment
202
. These accessed memory cells have a row address which corresponds to the value of the received X-address signal and column addresses which correspond to the value of the received Y-address signal (Y) for one bit and (Y+1) for the other bit.
In the 2-bit prefetch operation, the 2 prefetched bits, which have consecutive column address values, will be simultaneously accessed on I/O buses (RWBS
1
and RWBS
2
) by way of sense amplifiers (
301
and
302
) and thus a processor can gain access (read/write) to them on successive clock CLK cycles.
Referring now to FIG.
16
(
a
), a timing diagram illustrating the 2-bit prefetch read operation of the SDRAM of
FIG. 15
is set forth. In the read operation, a row address signal (not shown) and column address signal (not shown) are applied externally to the SDRAM synchronously with the clock signal CLK having a period of Tclk. The row address signal activates a word line in each memory cell segment (
201
and
202
). The read operation is a 4-bit burst read with the beginning bit identified by the externally applied row and column address signals. When data in the form of a burst is written to or read from a SDRAM in a prefetch mode, the address values accessed by the column switch lines (YSW
1
and YSW
2
) will differ depending whether a sequential or interleaved count mode is used as designated by an external control signal and the externally applied column address. For simplicity, it is assumed that the SDRAM is operating in the sequential count mode and that the least significant bit of the externally applied column address is a zero. The accessed column addresses A
1
-A
4
are sequential addresses with one bit increment between each.
Given the above conditions address A
1
is an even number, thus at time t
1
a column switch line from the group of column switch lines YSW
1
which corresponds to address A
1
is activated. Also at time t
1
a column switch line from the group of column switch lines YSW
2
which corresponds to address A
2
(=A
1
+1) is activated. DATA
1
and DATA
2
from memory cell segments
201
and
202
are thus output to I/O buses RWBS
1
and RWBS
2
respectively after a circuit propagation delay from t
1
.
Two clock CLK cycles later at time t
3
another column switch line from the group of column switch lines YSW
1
which corresponds to address A
3
(=A
1
+2) is activated. Also at time t
3
a column switch line from the group of column switch lines YSW
2
which corresponds to address A
4
(=A
1
+3) is activated. Thus, DATA
3
and DATA
4
from memory cell segments
201
and
202
are thus output to I/O buses RWBS
1
and RWBS
2
respectively after a circuit propagation delay from t
3
.
The data on the I/O buses RWBS
1
and RWBS
2
(first DATA
1
and DATA
2
and then DATA
3
and DATA
4
) are alternately latched at a predetermined timing synchronously with the clock signal CLK, and then sequentially output externally as data signals DQ synchronously with and on sequential CLK cycles.
The change of the activation of the column switch lines YSW
1
and YSW
2
(from A
1
to A
3
or from A
2
to A
4
) during the burst cycle is performed synchronously with the external clock signal CLK by circuitry within the Y-address buffer decoder
100
and controlled by a control circuit on the SDRAM (not shown).
For the 2-bit prefetch mode as shown in FIG.
16
(
a
) it takes two CLK cycles to access each group of prefetched data onto I/O buses (RWBS
1
and RWBS
2
). However, data signals DQ are output every CLK cycle synchr

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2960758