Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-03-15

2002-10-29

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189070, C365S189120, C365S230040

Reexamination Certificate

active

06473358

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and, more particularly, to a technique which is effective when used in a column selecting operation for the bursting actions of a synchronous dynamic RAM (Random Access Memory).
The synchronous DRAM (Dynamic RAM) is provided on a chip with an address counter for performing bursting actions. The synchronous DRAM is standardized to include an input unit for receiving an external address; an address counter for calculating an address to be used in a next cycle from the received address; a redundant address comparator; a pre-decoder arranged in parallel with the redundant address comparator; an output buffer for controlling the pre-decoder output on the basis of the redundant comparison result; and a column decoder, as recited in the order of signal propagations.
A synchronous DRAM, which is provided with an address shift register at the downstream stage of the pre-decoder and the redundant circuit to form an address signal for a burst action by its shifting action, so as to speed up the column selecting action, has been disclosed in Japanese Patent Laid-Open No. 275073/1994 or 320269/1997 (corresponding to U.S. Pat. No. 6,009,038).
SUMMARY OF THE INVENTION
In accordance with the speed-up of the operating frequency of a MPU (Micro Processor Unit), there has been a demand to raise the speed of the DRAM. In the standard circuit construction, which is provided with an address counter for calculating an address to be used in a next cycle from the address of an input unit for receiving an external address, however, the address cannot be advanced until the command decoder generates a column action signal, so that fast access is delayed. In the synchronous DRAM disclosed in the aforementioned Patent publication, therefore, the speed-up of the fast access and the count-up of the address can be realized by a shifting action because a shift register is disposed at the downstream stage of the pre-decoder. Thus, the cycle can be speeded up.
However, the synchronous DRAM as disclosed is able to cope with only the burst mode of a simple shifting action, but not an interleave action mode demanding a complex change in the address for an initial address. For a burst length of 8, for example, the interleave action mode is
0
→
1
→
2
→
3
→
4
→
5
→
6
→
7
as in the sequential action mode, if the value is 0. If the initial value is 1, however, the mode is
1
→
0
→
3
→
2
→
5
→
4
→
7
→
6
. If the initial value is 2, the mode is
2
→
3
→
0
→
1
→
6
→
7
→
4
→
5
. Thus, the shift registers, as disclosed in the above-mentioned publications cannot solve the problem in the least. Specifically, Japanese Patent Laid-open No. 320269/1997 has failed to take into consideration the redundant circuit, and Japanese Patent Laid-Open No. 275073/1994 has a problem in that the circuit scale is enlarged by the provision of the redundant circuit with a similar shift register.
An object of the invention is to provide a semiconductor memory device which can realize various burst actions while speeding up the actions.
Another object of the invention is to provide a semiconductor memory device which can realize simplification of the redundant circuit while speeding up the actions.
The aforementioned and other objects and novel features of the invention will become apparent from the following description to be made with reference to the accompanying drawings.
A summary of representative aspects of the invention to be disclosed will be briefly described in following. Specifically, a semiconductor memory device comprises a memory array including a plurality of word lines and a plurality of bit lines; and a column address decoder for selecting a predetermined bit line from the plurality of bit lines. The column address decoder includes first and second pre-decoders corresponding to high-order and low-order addresses, respectively; a shift register for using the output signal of the second pre-decoder as an initial value; and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal obtained through the output circuit. The shift register includes a first shift register for an even address and a second shift register for an odd address. Thus, the continuous selecting signals of the bit lines, as composed of a sequential action and an interleave action, are formed on the basis of the initial value by combining its up and down shifting actions.
The summary of the representative embodiments of the invention to be disclosed will be briefly described in the following. Specifically, a semiconductor memory device comprises: a memory array including a plurality of word lines, a plurality of bit lines and a redundant bit line; and a column address decoder for selecting a predetermined bit line from the plurality of bit lines. The column address decoder includes: first and second pre-decoders corresponding to high-order and low-order addresses, respectively; a shift register for using the output signal of the second pre-decoder as an initial value; and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. A redundant circuit for switching to the redundant bit line includes: a comparator for comparing such one of the faulty addresses stored in the memory circuit as corresponds to the high-order address and the address signal inputted; a redundant pre-decoder for decoding the low-order address of the faulty addresses; and a coincidence detect circuit for detecting the compared coincidence output of the comparator and a coincidence between the individual outputs of the redundant pre-decoder and the second pre-decoder. A predetermined bit line is selected from the redundant bit lines by the redundant bit line select circuit in response to the detected signal of the coincidence detect signal in place of the select signal formed in the column address decoder.


REFERENCES:
patent: 5572463 (1996-11-01), Akaogi et al.
patent: 5805504 (1998-09-01), Fujita
patent: 5852585 (1998-12-01), Koshizuka
patent: 6009038 (1999-12-01), Koshizuka
patent: 6011751 (2000-01-01), Hirabayashi
patent: 6088291 (2000-07-01), Fujioka et al.
patent: 6240048 (2001-05-01), Matsubara
patent: 6335901 (2002-01-01), Morita et al.
patent: 6-275073 (1994-09-01), None
patent: 9-320269 (1997-12-01), None

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