Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-03-20

2002-05-14

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189011, C365S190000

Reexamination Certificate

active

06388938

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 USC §119 to Japanese Patent Application No. 2000-89702, filed on Mar. 28, 2000, the contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor memory device.
2. Description of Related Art
Generally, in the design for semiconductor memory devices such as SRAMs (Static Random Access Memories), products, which have different bit configurations even if their storage capacities are the same, are designed at the same time at a customer's request. For example, with respect to an SRAM having a storage capacity of 9 Mbits, its bit configurations including redundant divisions are various configurations, such as 256 kwords×36 bits or 512 kwords×18 bits, in accordance with its uses.
Usually, such products having different bit configurations are realized by changing a wiring layer by switching a mask for a specific in the same chip.
The layout of a memory cell array of a typical SRAM is shown in FIG.
4
. In this SRAM, a memory cell array is divided into two cell arrays A
r1
and A
r2
on a chip. Each of the cell arrays A
ri
(i=1, 2) comprises k section parts S
1
, . . . , S
k
. Each of the section parts S
i
(i=1, . . . , k) of the cell array A
r1
has n input/output part I/O
1
, . . . , I/O
n
, and each of the section parts S
j
(j=1, . . . , k) of the cell array A
r2
has n input/output parts I/O
n+1
, . . . , I/O
2n
.
The construction of a conventional semiconductor memory device having the layout of the memory cell shown in
FIG. 4
is shown in FIG.
5
. In this conventional semiconductor memory device, the n input/output parts I/O
1
, . . . , I/O
n
of each of the section parts S
i
(i=1, . . . , k) of the cell array A
r1
are connected to one ends of first through n-th output signal lines, and the n input/output parts I/O
1
, . . , I/O
n
of each of the section parts S
j
(j=1, . . . , k) of the cell array A
r2
are connected to one ends of (n+1)-th through 2n-th output signal lines. That is, the j-th (j=1, . . . , n) input/output part I/O
j
of the section part S
i
(i=1, . . . , k) of the cell array A
r1
is connected to one end of the j-th output signal line, and the j-th (j=1, . . . , k) input/output part I/O of the section part S
i
(i=1, . . . , k) of the cell array A
r2
is connected to one end of the (n+j)-th output signal line.
The above described semiconductor memory device also has 2n output control circuits
3
1
, . . . ,
3
2n
, and 2n output transistor circuits (which will be also hereinafter referred to as output T
r
circuits)
5
1
, . . . ,
5
2n
. The other end of the i-th (i=1, . . . , 2n) output signal line is connected to the output control circuit
3
i
.
Therefore, the i-th (i=1, . . . , n) input/output part I/O
i
of each of the section parts S
1
, . . . , S
k
of the cell array A
r1
is connected to the output control circuit
3
i
via the i-th output signal line, and the i-th (i=1, . . . , n) input/output part I/O
i
of each of the section parts S
1
, . . . , S
k
of the cell array A
r2
is connected to the output control circuit
3
n+i
via the (n+i)-th output signal line. The output of the output control circuit
3
i
(i=1, . . . , 2n) is fed to a corresponding output Tr circuit
5
i
.
In the semiconductor memory device shown in
FIG. 5
, the total wiring capacity of the respective output signal lines is constant with respect to any one of the section parts or any one of the input/output parts.
The construction of another conventional semiconductor memory device having the layout of the memory cell array shown in
FIG. 4
is shown in FIG.
6
. In this semiconductor memory device, an additional signal Ad is newly introduced into the semiconductor memory device shown in
FIG. 5
, to select a cell array A
r1
by the additional signal Ad and to select a cell array A
r2
by the additional signal /Ad which is the inverted signal of the additional signal Ad. In addition, n selecting circuits
4
1
, . . . , 4
n
are newly provided between 2n output control circuits
3
1
, . . . ,
3
2n
and n output Tr circuits
5
1
, . . . ,
5
n
.
The selecting circuit
4
i
(i=1, . . . , n) is designed to select the output of the output control circuit
3
i
or the output of the output control circuit
3
n+i
on the basis of the additional signal Ad to transmit the selected output to a corresponding output Tr circuit
5
i
.
With this construction, assuming that the word length of the semiconductor memory device shown in
FIG. 5
is W
L
, the semiconductor memory device shown in
FIG. 6
is a product having a bit configuration of 2W
L
×n. Furthermore, the semiconductor memory device shown in
FIG. 5
is a product having a bit configuration of W
L
×2n.
The conventional semiconductor memory device shown in
FIG. 6
uses half (=n/2) the n output transistor circuits on the side of the cell array A
r1
, and does not use the remaining half the output transistor circuits, although this depends on the pin arrangement of the package. This is the same with respect to the n output transistor circuits on the side of the cell array A
r2
. That is, the semiconductor memory device uses half the n output transistor circuits
5
1
, . . . ,
5
n
in
FIG. 5
, e.g., the output transistor circuits
5
1
, . . . ,
5
n/2
, as the output transistor circuits of the cell array A
r1
of
FIG. 6
, and uses half the n output transistor circuits
5
n+1
, . . . ,
5
2n
, e.g., the output transistor circuits
5
n+1
, . . . ,
5
3n/2
, while it does not use the other transistor circuits.
Since the layout shown in
FIG. 4
is used when the semiconductor memory device shown in
FIG. 6
is produced by changing an AL wiring such as an AL master slice, it is required to newly draw an output line
15
of each of the output control circuits
3
i
(i=1, . . . , 2n) as shown in FIG.
6
.
For that reason, in the conventional semiconductor memory device shown in
FIG. 6
, the characteristics of access time are deteriorated by the delay time of the wiring
15
in comparison with the construction of the semiconductor memory device shown in FIG.
5
. This deterioration of the characteristics of access time is more remarkable as the capacity of the memory device increases since the length of the drawn wiring increases.
The construction of a further conventional semiconductor memory device having the layout of the memory cell shown in FIG.
4
is shown in FIG.
7
. In this semiconductor memory device, an additional signal Ad is newly introduced into the semiconductor memory device shown in
FIG. 5
, to select a cell array A
r1
by the additional signal Ad and to select a cell array A
r2
by an additional signal /Ad. The i-th (i=1, . . . , n) input/output part I/O
i
of each of k section parts S
1
, . . . , S
k
of the cell array A
r1
is connected to an output selecting circuit
2
i
via the first output signal line, and the i-th (i=1, . . . , n) input/output part I/O
i
of each of k section parts S
1
, . . . , S
k
of the cell array A
r2
is connected to the output selecting circuit
2
i
via the (n+i)-th output signal line.
Each of the output selecting circuits
2
i
(i=1, . . . , n) is designed to select the output of the cell array A
r2
, which is transmitted via the i-th output signal line, or the output of the cell array A
r2
which is transmitted via the (n+i)-th output line, on the basis of the additional signal Ad to transmit the selected output to a corresponding output transistor
5
i
.
The semiconductor memory device shown in
FIG. 7
has output control circuits
2
1
, . . . ,
2
n
, and output transistor circuits
5
1
, . . . ,
5
n
. The semiconductor memory device shown in
FIG. 7
is a product having a bit configuration of 2WL×n similar to the semiconductor memory device shown in FIG.
6
.
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