Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-04-17

2002-04-09

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185200, C365S210130

Reexamination Certificate

active

06370060

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device for reading data after comparing a voltage level of data read from a memory cell and a reference voltage level and amplifying the difference between the levels, such as, for example, a mask ROM, an EPROM, a flash memory and a ferroelectric memory.
2. Description of the Related Art
Conventionally, this type of semiconductor memory device reads data by comparing a voltage level of data read from a memory cell and a preset reference voltage level and amplifying the difference between the levels.
FIG. 6
is a circuit diagram of a semiconductor memory device
100
as an example of conventional semiconductor memory devices. As shown in
FIG. 6
, the semiconductor memory device
100
includes a memory cell array
110
, a row decoder
120
for outputting a signal to one of a plurality of word lines W
0
through Wn which is selected by an address signal AS, and a column decoder
130
for selecting one of a plurality of bit lines B
00
through B
0
n
by outputting a signal to one of a plurality of column selection signal lines Ba
0
through Bam which is selected by the address signal AS.
The memory cell array
110
includes a plurality of memory cells MC each formed of a MOS transistor arranged in a matrix, the plurality of word lines W
0
through Wn, and the plurality of bit lines B
00
through B
0
n
. In a row direction, n memory cells MC are provided, and a column direction also, n memory cells MC are provided.
Control gates G of the n memory cells MC on each row are commonly connected to the corresponding word line W. In more detail, the control gates G of the memory cells MC
000
through MC
0
n
0
on row 0 are commonly connected to the word line W
0
. The control gates G of the memory cells MC
00
n
through MC
0
nn
on row n are commonly connected to the word line Wn.
Drains D of the n memory cells MC on each column are commonly connected to the corresponding bit line B. In more detail, the drains D of the memory cells MC
000
through MC
00
n
on column
0
are commonly connected to the bit line B
00
. The drains D of the memory cells MC
0
n
0
through MC
0
nn
on column n are commonly connected to the bit line B
0
n
. Sources S of the memory cells MC in each column are commonly connected and grounded.
Outputs of the row decoder
120
are respectively connected to the word lines W
0
through Wn. In accordance with the value of a row selection signal of an input address signal AS, the row decoder
120
outputs a word line selection signal to a selected word line W.
The column decoder
130
includes a column pre-decoder
131
and switching transistors ST
00
through ST
0
n
each forming a switching circuit. Each switching circuit is turned on by a column selection signal sent from the column pre-decoder
131
.
For reading data from the memory cell array
110
, the column pre-decoder
131
outputs a column selection signal, decoded from the input address signal AS, to one of the column selection signal lines Ba
0
through Bam.
The switching transistors ST
00
through ST
0
n
are respectively connected to the bit lines B
00
through B
0
n
. The column selection signal sent from the column pre-decoder
131
is sent to a gate of one of the switching transistors ST which is selected by the column selection signal, and the switching transistor ST which receives the column selection signal connects the corresponding bit line B to a memory bit line BB
0
.
The semiconductor memory device
100
further includes a switching circuit
140
for adjusting a resistance value of a reference bit line BBr, a reference circuit
150
for setting a reference voltage level, a sense block
160
for comparing the set reference voltage level and a voltage level from a memory cell MC and amplifying the difference between the levels so as to output the memory data, and an output circuit
170
for sending the output from the sense block
160
to the outside of the semiconductor memory device
100
.
The switching circuit
140
includes a switching transistor STref. An ON resistance of the switching transistor STref is controlled so that a total resistance value of the memory bit line BB
0
and selected bit line B (B
00
through B
0
n
) equals the reference bit line BBr. In other words, when a voltage having an equal value to that of an active voltage sent to the selected column selection signal lines Ba is input to a gate of the switching transistor STref, an ON resistance of the selected switching transistor ST in the column decoder
130
and the ON resistance of the switching transistor STref are equal to each other.
The reference circuit
150
includes a reference word line (Wref) control circuit
151
for receiving a read control signal and a reference cell Tref. The reference cell Tref includes a control gate G connected to a reference word line Wref, a drain D connected to the reference bit line Bref, and a source S which is grounded.
The sense block
160
includes a precharge circuit
162
connected to the memory bit line BB
0
through a switch
161
, a bias circuit Bias
0
connected to the memory bit line BB
0
, a precharge circuit
164
connected to the reference bit line BBr through a switch
163
, a bias circuit Biasr connected to the reference bit line BBr, and a sensing amplifier SA. One of two inputs (i.e., input B
0
) of the sensing amplifier SA is connected to an output of the bias circuit Biaso, and the other input (i.e., input Br) of the sensing amplifier SA is connected to an output of the bias circuit Biasr. For reading data, the sensing amplifier SA compares the preset reference voltage level and the voltage level of data of the memory bit line BB
0
and amplifies the difference between the voltage levels, which is output to the outside of the semiconductor memory device
100
.
The precharge circuit
162
performs a precharge operation so as to charge, at a high speed, a floating capacitance (or a parasitic capacitance) of the bit line B selected by the switching transistors ST
00
through ST
0
n
. When the floating capacitance is fully charged, the precharge circuit
162
turns off the switch
161
to stop the precharge operation. The precharge circuit
164
has the same structure as that of the precharge circuit
162
.
The bias circuit Bias
0
includes a feedback circuit
165
, a transistor T
1
(n-channel transistor for a transfer gate), and a reference resistance R. The feedback circuit
165
includes a reference resistance r and a transistor t which are connected in series as shown in
FIG. 7. A
connection point a′ between the reference resistance r and the transistor t is connected to a gate of the transistor T
1
. A gate of the transistor t is connected to the memory bit line BB
0
. The feedback circuit
165
can have a different configuration from the configuration shown in FIG.
7
. The bias circuit Biasr includes a feedback circuit
165
and a transistor T
2
, and has substantially the same configuration as that of the bias circuit Bias
0
.
The output circuit
170
includes an output control circuit
171
and an output buffer
172
for temporarily storing data. The output circuit
170
outputs the outputs from the sensing amplifier SA to the outside of the semiconductor memory device
100
sequentially.
The semiconductor memory device
100
having the above-described structure operates as follows.
An address signal AS is input to the row decoder
120
. In accordance with the value of a row selection signal of the input address signal AS, the row decoder
120
sends a word line selection signal to a selected word line W (more specifically, to the control gates G of the memory cells MC of the selected row). The address signal is also input to the column pre-decoder
131
. In accordance with the value of a column selection signal of the input address signal AS, the column pre-decoder
131
sends a column selection signal to a selected column selection signal line Ba. Then, the column selection signal is output to the gate of the corresponding switching transistor

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