Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-03-20

2002-05-14

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S236000, C365S238500

Reexamination Certificate

active

06388937

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in Japanese Patent Application No. 2000-89561 filed on Mar. 28, 2000 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of The Invention
The present invention relates generally to a synchronous type semiconductor memory device which operates in a burst mode in synchronism with a clock signal. More specifically, the invention relates to a synchronous type semiconductor memory device wherein a data reading operation corresponding to read latency is accelerated.
2. Related Background Art
As the working speed of CPUs for use in computers is accelerated every year, rapidly operatable SRAMs are often being used as cache memories required to follow the operation of rapid CPUs. In such cases, SRAMs used as cache memories are often synchronous SRAMs which operate in synchronism with external clocks.
In order to allow a more rapid operation than the operation in a usual random access, the following two architectures are sometimes adopted.
First, there is a burst sequence for sequentially automatically generating addresses of a predetermine bit number on the basis of a predetermined sequence in synchronism with clocks in the subsequent operation cycle in accordance with an initial address inputted from the outside. In this burst operation, it is not required to incorporate addresses from the outside every operation cycle, and a rapid operation is realized by assigning the burst address to the fastest system in a memory cell selecting path.
Secondary, there is a read latency which is the setting how many cycles after a cycle in which an address is inputted from the outside, data should be outputted. By increasing the number of cycles, i.e., a read latency, in a predetermined period of time until the initial data are outputted after an address is inputted from the outside, it is possible to increase the operating frequency.
FIG. 1
is a block diagram showing the construction of a conventional synchronous SRAM.
The conventional synchronous SRAM comprises: n×m memory cells C
11
, . . . , Cnm provided in the form of a matrix; a row decoder RD for outputting a row selecting signal for selecting one of the memory cells in each row; word lines WL
1
, . . . , WLn, connected to the memory cells in each row and the row decoder RD, for transmitting the row selecting signal; a column decoder CD for decoding an input address to a column selecting signal for selecting one of the memory cells in each column, to output the column selecting signal; a burst counter BC for sequentially automatically generating an address of a predetermined bit number in synchronism with a clock on the basis of a predetermined sequence in the subsequent operation cycle in accordance with the inputted initial address, to output the generated address to the column decoder; a column register CRG for outputting the column selecting signal, which is inputted from the column decoder CD, at a predetermined timing; column selecting signal lines YS
1
, . . . , YSm, connected to the column register CRG, for transmitting the column selecting signal; bit line pairs BL
1
, BL
1
B, . . . , BLm, BLMB, which are connected to the memory cells in each column and which comprise bit lines and inversion-side bit lines for transmitting a data signal when data are inputted to and outputted from the memory cells; bit line peripheral circuits CA
1
, . . . , CAm which are connected to the respective bit line pairs and the respective column selecting signal lines and to which the column selecting signal is inputted, the data signal transmitted by the bit line pairs being inputted to and outputted from the bit line bit line peripheral circuits CA
1
, . . . , CAm; a data bus pair comprising a data bus DL and inversion-side data bus DLB which are connected to the respective bit line pairs via the respective bit line peripheral circuits; a reading circuit RC for reading data out of the respective memory cells via the bit line pairs, the bit line peripheral circuits and data bus pair, to amplify and output the read data; a data output register RGOUT for outputting data, which are amplified by the reading circuit RC, to an input/output port I/O at a predetermined timing; a data input register RGIN for outputting data, which are inputted from the input/output port I/O, at a predetermined timing; and a writing circuit WC for amplifying and outputting data, which are inputted from the data input register RGIN, to write the data in each of the memory cells via the data bus pair, bit line peripheral circuits and bit line pairs.
As an example of the construction of each of the memory cells C
11
, . . . , Cnm, the construction of the first-row, first-column memory cell C
11
will be described. The memory cell C
11
comprises: first and second inverters INV
11
a
and INV
11
b
which are connected to each other as a cycle; a first transfer switch TS
11
comprising an N-channel MOS transistor which is provided between the first-column bit line BL
1
and the input node of the first inverter Inv
11
a
, and the gate of which is connected to the first-row word line WL
1
; and a first inversion-side transfer switch TS
11
B comprising an N-channel MOS transistor which is provided between the first-column inversion-side bit line BL
1
B and the input node of the second inverter INV
11
b
, and the gate of which is connected to the first-row word line WL
1
. The first and second inverters INV
11
a
and INV
11
b
constitute a flip-flop. Each of the other memory cells has the same construction.
Each of the bit line peripheral circuits CA
1
, . . . , CAm comprises: a column switch for connecting and disconnecting between the respective bit lines and inversion-side bit lines, and the data bus DL and inversion-side data bus DLB; a pre-charging circuit for pre-charging the respective bit lines and inversion-side bit lines; and an equalizing circuit for equalizing the respective bit lines and inversion-side bit lines. The column selecting signal is inputted to the column switch, so that the connection and disconnection between the respective bit lines and inversion-side bit lines, and the data bus DL and inversion-side data bus DLB is controlled.
FIG. 2
is a timing chart showing the waveforms of principal signals in the conventional synchronous SRAM shown in FIG.
1
. The signal waveforms shown in
FIG. 2
include the waveforms of a clock signal CLK, an address signal Add, a row selecting signal for the first-row word line WL
1
, a potential of each of the bit lines BL and inversion-side bit lines BLB, column selecting signals for the column selecting signal lines YS
1
, YS
2
, YS
3
and YS
4
, and a data signal DATA in the input/output port I/O.
Referring to
FIG. 2
, a data reading operation in the conventional synchronous SRAM will be described below.
When an address signal Add is inputted in synchronism with the leading edge of a clock signal CLK at a start time t
0
in the initial cycle T
1
during a reading operation in a memory cell, decode signals are generated by the row decoder RD and column decoder CD as a row selecting signal and a column selecting signal, respectively.
Assuming herein that a word line selected by the row selecting signal is the first-row word line WL
1
, the transfer switches of the memory cells C
11
, C
12
, . . . , C
1
m
connected to the first-row word line WL
1
are turned on by the row selecting signal transmitted by the first-row word line WL
1
. Then, a current flows into the low potential side of the flip-flops constituting the selected memory cells via the transfer switches. As a result, the potential of one of the bit line pairs BL and BLB, which have been pre-charged at a high potential and equalized, is lowered to cause a potential difference between the pair of bit lines BL and BLB. At this time, the reading circuit RC holds a preparatory state in which data read in the preceding reading operation are canceled.
In the se

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2837032