Semiconductor memory device

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

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Details

C365S230080, C365S194000

Reexamination Certificate

active

07391670

ABSTRACT:
A semiconductor memory device is provided. The semiconductor memory device includes an active commander for generating an active command upon receiving a plurality of control signals, a first signal generator configured to receive the active command, and generate a first latch signal for latching information associated with activation of the active command, a second signal generator configured to receive the first latch signal and a chip selection signal, generate a word-line activation signal and activation-information signal when the first latch signal and the chip selection signal are simultaneously enabled, and a reset controller configured to receive a second latch signal, the word-line activation signal, and the activation-information signal, and control the first signal generator to reset the first latch signal using the received signals.

REFERENCES:
patent: 6272057 (2001-08-01), Koshikawa
patent: 6333892 (2001-12-01), Hamamoto et al.
patent: 6525989 (2003-02-01), Mizugaki et al.
patent: 6545943 (2003-04-01), Mizugaki et al.
patent: 10-334699 (1998-12-01), None
patent: 1020000020619 (2000-04-01), None
patent: 1020030089231 (2003-11-01), None
patent: 1020040073789 (2004-08-01), None

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