Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2011-06-28

2011-06-28

Blum, David S (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

C257S208000, C257SE29166

Reexamination Certificate

active

07968917

ABSTRACT:
There is provided a semiconductor memory device including: a first wiring layer; a second wiring layer; a third wiring layer; a memory array region; a first gate array region being formed at a region at which the first wiring layer, the second wiring layer and the third wiring layer can be used in wiring of the plural unit cells; and a second gate array region being formed at a region at which two wiring layers that are the first wiring layer and the second wiring layer can be used in wiring of the plural memory cells, and the plural unit cells are arrayed so as to be separated at an interval needed for placement, by using the first wiring layer, of wiring that should be placed by using the third wiring layer.

REFERENCES:
patent: 2009/0039918 (2009-02-01), Madurawe
patent: 2009/0194768 (2009-08-01), Leedy
patent: 2009/0243650 (2009-10-01), Madurawe
patent: 2008-071865 (2008-03-01), None

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