1989-12-11
1991-02-26
Prenty, Mark
357 54, 357 59, H01L 2978, H01L 2934, H01L 2904
Patent
active
049965727
ABSTRACT:
A semiconductor memory device containing a number of memory cells each having a floating gate, an erase gate, and a control gate. In a data erasure mode, electrons are discharged from the floating gate into the erase gate electrode. An insulating film interlaid between the erase gate and the control gate has a three-layered structure consisting of a silicon oxide film, a silicon nitride film, and a silicon oxide film.
REFERENCES:
patent: 4437172 (1984-03-01), Masuoka
patent: 4437174 (1984-03-01), Masuoka
patent: 4466081 (1984-08-01), Masuoka
Masuoka et al., A Flash E.sup.2 Prom Cell Using Triple Polysilicon Technology, Proceedings of the IEEE International Electron Devices Meeting, Dec. 9-12, 1984.
Hori Masayuki
Tanaka Shin-ichi
Tozawa Noriyoshi
Kabushiki Kaisha Toshiba
Prenty Mark
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