Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Reexamination Certificate
2011-01-18
2011-01-18
Nguyen, Dang T (Department: 2824)
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
C365S145000, C365S063000
Reexamination Certificate
active
07872939
ABSTRACT:
A semiconductor memory device includes: a first address buffer configured to be used in a test mode and a normal mode and to receive more addresses in the test mode than in the normal mode; and a second address buffer configured to be used in the normal mode and disabled in the test mode.
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patent: 5561639 (1996-10-01), Lee et al.
patent: 5809228 (1998-09-01), Langendorf et al.
patent: 6909624 (2005-06-01), Sadakata et al.
patent: 2006/0077703 (2006-04-01), Miyakawa et al.
patent: 10-0646202 (2006-11-01), None
Blakely & Sokoloff, Taylor & Zafman
Hynix / Semiconductor Inc.
Nguyen Dang T
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