Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2011-01-11

2011-01-11

dinh, Son (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185200, C365S185110, C365S063000

Reexamination Certificate

active

07869274

ABSTRACT:
A memory includes: first sense amplifiers arranged in a first interval of an arrangement of memory cell arrays, each being connected to first bit lines corresponding to two memory cell arrays provided at both sides of the first sense amplifier; second sense amplifiers arranged in a second interval of the arrangement of the memory cell arrays, each being connected to second bit lines corresponding to two memory cell arrays at both sides of the second sense amplifier; edge arrays provided beside both ends of an arrangement of the memory cell arrays, the edge arrays generating only the reference data; and edge sense amplifiers provided between the arrangement of the memory cell arrays and the edge arrays, wherein the edge sense amplifier detects data from the memory cell array at one end of the memory cell arrays based on the reference data from one of the edge arrays.

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Takashi Ohsaw, et al., “An 18.5ns 128Mb SOI DRAM with a Floating Body Cell”, ISSCC Digest of Technical Papers, Session 25, Dynamic Memory, Feb. 2005, 3 Pages.
Tsugio Takahashi, et al., “A Multigigabit DRAM Technology with 6F2Open-Bitline Cell, Distributed Overdriven Sensing, and Stacked-Flash Fuse”, IEEE Journal of Solid-State Circuits, vol. 36, No. 11, Nov. 2001, pp. 1721-1727.

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