Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-12-15

2001-02-13

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000

Reexamination Certificate

active

06188630

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a synchronous semiconductor memory device.
Description of the Related Art
A synchronous DRAM, one of the conventional synchronous semiconductor memory devices, comprises: a plurality of memory cells; a plurality of bit lines to which are respectively given potentials based on the data sent from the plurality of memory cells; a plurality of sense-amplifiers which respectively amplify the potential of the plurality of bit lines; and a plurality of column switches respectively connected between the plurality of bit lines and a plurality of data lines.
In the synchronous DRAM, the column-selection signal is given to sequentially select column switches, so that potentials based on the data of the memory cells that correspond to thus selected column switches are sequentially given to data lines.
The conventional synchronous DRAM sequentially outputs to the external the data based on a potential sent to the data line ,in response to the leading edge of the clock signal.
The conventional synchronous DRAM turns ON the column switches one by one to sequentially send to the data line a potential based on the data of mutually adjacent two memory cells, which therefore takes a considerably long time to do so.
With this, in the array configuration of the conventional synchronous DRAMs, in order to implement such a double-data-rate synchronous DRAM which outputs a potential based on the data of mutually adjacent two memory cells, it is necessary to lengthen the period of the clock signal, thus leading to a problem in that the DRAM cannot operate speedily.
Further, the synchronous DRAM includes in each memory block a great many sense-amplifiers. Those sense-amplifiers, each of which is connected to the power supply to activate itself, have mutually different distances between the power supply and themselves.
Therefore, the sense-amplifier most distant from the power supply suffers from a voltage droop due to a large wiring resistance between itself and the power supply.
This leads to decreases in the speed for the sense-amplifier to amplify the potential of bit lines, thus causing a problematical drop in the operational margin of the synchronous DRAM as a whole.
SUMMARY OF THE INVENTION
To solve the above-mentioned problems, the present invention provides a semiconductor memory device which comprises first, second, third, and fourth memory blocks each of which comprises: word lines; memory cells connected to the above-mentioned word lines, to store data therein; bit lines to which are given potentials based on data stored in the above-mentioned memory cells, when the above-mentioned word lines are selected; and sense-amplifiers which amplify the potential sent to the above-mentioned bit lines, further comprising: a first transfer circuit which is coupled between the above-mentioned bit lines of the above-mentioned first memory block and first data lines, to be conductive in response to the signal value of a first column-selection signal and a first block-selection signal; a second transfer circuit which is coupled between the above-mentioned bit lines and first data lines and a second data line and first data lines, to be conductive in response to the signal value of a second column-selection signal and the signal value of a second block-selection signal; a third transfer circuit which is coupled between the above-mentioned bit lines of the above-mentioned third memory block and the above-mentioned first data line, to be conductive in response to the signal value of a third column-selection signal and the signal value of the above-mentioned second block-selection signal; and a fourth transfer circuit which is coupled between the above-mentioned bit lines of the above-mentioned fourth memory block and the above-mentioned second data line, to be conductive in response to the signal value of a fourth column-selection signal and the value of the above-mentioned first block-selection signal.


REFERENCES:
patent: 5495444 (1996-02-01), Okubo et al.
patent: 5862095 (1999-01-01), Takahashi et al.
patent: 5883851 (1999-03-01), Lee
patent: 5970019 (1999-10-01), Suzuki et al.

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2613275