Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-08-30

2001-10-09

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S189011

Reexamination Certificate

active

06301144

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-246173, filed Aug. 31, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device. More particularly, the invention relates to a compressed-data test to be performed on DRAM (Dynamic Random Access Memory).
In recent years, the storage capacity of DRAMs has increased to meet the demand in the market, thanks to the advancement in the manufacturing technology. The greater the storage capacity of a memory chip, the longer the time required to test the memory chip. This is because, data must be written into and read from all memory cells (bits) in the test. If the storage capacity increases four times, four times as much time is required to test the memory chip.
To shorten the test time, the compressed-data test is effected and useful as is known in the art. In the compressed-data test, a number of bits are accessed at a time, and the data consisting of these bits is compressed into data consisting of a smaller number of bits, such as eight bits or four bits. It is then determined whether each bit indicates that the corresponding bits stored in the memory cells one cell are identical in polarity or that that the corresponding bits are not identical in polarity. The more bits (e.g., 64 bits or 128 bits) are accessed simultaneously, the shorter the test time.
Assume that 64 bits are accessed at a time in a memory chip designed such that data is read from it in units of four bits, and that these bits are compressed into a data item consisting of four bits. Then, the test time is reduced to {fraction (1/16)}. Namely, 64 bits are accessed in the memory chip, though it seems as if 4-bit data were accessed.
If all bits constituting the data to be compressed are of the same polarity, “1” will be read from the memory chip. Otherwise, “0” will be read from the memory chip. To utilize this data-compressing method, bits of the same polarity must be written into the memory cells which will be accessed at the same time.
The conventional data-compressing method will be described in greater detail, with reference to
FIG. 1
that is a schematic representation of a memory chip.
As shown in
FIG. 1
, each bank
101
of the memory cell array comprises a plurality of cell sections
102
and a plurality of sense amplifiers (S/A)
103
. Any two adjacent sense amplifiers
103
are arranged on two sides a cell section
102
, respectively. Word lines WL extend parallel over the cell section
102
, and bit lines BL/bBL extend at right angles to the word lines WL, over the bank
101
, too. Memory cells MC are arranged at the intersections of the word lines WL and the bit lines BL/bBL; they are arranged in rows and columns, forming a matrix. Data-line pairs
104
are connected to the sense amplifiers
103
. Each data-line pairs
104
can be selected in accordance with a column address. Amplifiers
105
are provided outside the bank
101
and connected to the data-line pairs
104
, respectively. Each amplifier
105
has two output terminals, to which two signal lines RD and bRD are connected at one end. The signal lines RD and bRD make a signal-line pair
106
. The signal lines RD and bRD are connected at the other end to an output circuit (not shown) that is designed to output data from the memory chip.
While the memory chip remains in the normal operating mode, the sense amplifiers
103
can be activated. When activated, the sense amplifiers
103
read data from the memory cells MC. The data, thus read, is supplied the data-line pairs
104
that have been supplied through column-selecting lines selector (not shown). The signal representing the data and supplied via each data-line pair
104
is amplified by the amplifier
105
connected to the data-line pair
104
. The signal amplified is supplied to the output circuit through the signal-line pair
106
.
The least number of amplifiers
105
and the least number of signal-line pairs
106
, which should be activated, depend upon how many bits are simultaneously read from the memory cells MC provided in the bank
101
. If it is necessary to read at most four bits at a single access, four amplifiers
105
and four signal-line pairs
106
must be activated. Alternatively, five or more amplifiers
105
and five or more signal-line pairs
106
are activated, and four bits are read simultaneously or not simultaneously from the memory chip (this method of reading bits is known as “pre-fetch method”). In either case, the signal-line pairs
106
must be activated in at least the same number as the bits that should be read at a single access.
While the memory chip of
FIG. 1
remains in, for example, the compressed-data test, 64-bit data may be compressed into 4-bit data, thus accomplishing so-called {fraction (1/16)} data compression. More specifically, 64 amplifiers
105
and
64
signal-line pairs
106
are activated, thereby reading 64 bits from 64 memory cells MC, into which bits of the same polarity have been written. The 64 bits read are supplied to a coincidence
on-coincidence determining circuit (not shown), which compresses the 64-bit data into 4-bit data, wherein each bit indicates whether 16 bits are of the same polarity or not. That is, the circuit outputs a bit “1” if all 16 bits are of the same polarity, and a bit “0” if all 16 bits are not of the same polarity.
In this case, the memory chip need to have 64 signal-line pairs
106
, that is, as many signal-line pairs
106
as the number (64) of bits to be accessed, irrespective of the number (4) of bits into which the determining circuit compresses input data. While the memory chip remains in the normal operating mode, it suffice to use four signal-line pairs
106
(i.e., eight signal lines). As long as the chip remains in the compressed-data test mode, however, 64 signal-line pairs
106
(i.e., 128 signal lines) must be used. In the case where 128-bit data is compressed, 128 signal-line pairs
106
(i.e., 256 signal lines) must be used. The memory chip therefore needs to have a large wiring region to accommodate so many signal-line pairs.
To prevent an increase in the size of the wiring region, it is proposed that the signal lines be pre-charged so as to perform part of the function of the coincidence
on-coincidence determining circuit.
FIG. 2
shows a part of a conventional memory chip in which the signal lines are pre-charged to perform part of the function of the coincidence
on-coincidence determining circuit. This memory chip is so designed that at most four bits are accessed at a time and four signal-line pairs
106
(i.e., eight signal lines) are provided.
The memory chip of
FIG. 2
comprises NOR circuits
107
, each designed to determine whether the two input bits are identical or not, and an output circuit (not shown) for outputting data from the memory chip. The memory chip has as many signal-line pairs
106
as the bits to be read from the bank
101
at a single access. Each signal-line pair
106
is connected at one end to the output terminals of the amplifiers
105
, for supplying the bits, in so-called “increment” fashion. Each signal-line pair
106
is connected at the other end to one NOR circuit
107
and also to the output circuit (not shown).
While the memory chip remains in the normal operating mode, both signal lines RD and bRD of each pair
106
are pre-charged to high level “Hi” as shown in FIG.
3
A. If data “0” is read via any data-line pair
104
connected to the amplifier
105
which is connected to the signal-line pair
106
, one of the signal lines
106
(in this case, line RD) is driven at low level “Lo”. If data “1” is read via that data-line pair
104
, the other of the signal lines
106
(i.e., line bRD) is driven at low level “Lo”. In other words, each amplifier
105
discharges one signal line RD or other signal line bRD of the pair
106
, in accordance with the polarity of the data read via the data-line pair

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