Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-04-20

2001-12-25

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S201000, C365S222000, C365S236000, C365S230060

Reexamination Certificate

active

06333888

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to the semiconductor memory device having a memory cell array provided with a plurality of memory cells mounted in a matrix form and having a plurality of banks composed of circuits mounted around the memory cell array.
2. Description of the Related Art
As is well known, a DRAM (Dynamic Random Access Memory), one type of semiconductor memory device, is constructed of memory cell arrays in which memory cells each being composed of a MOS (Metal Oxide Semiconductor) transistor for switching (hereinafter referred to as a “switching transistor”) and of a memory capacitor are arranged in a matrix form. The memory capacitor is adapted to store one-bit data showing a “0” or “1” state depending on whether an electric charge is accumulated or not therein. A source electrode of the switching transistor constituting the memory cell is connected to one electrode of the memory capacitor. A gate electrode of the switching transistor is connected to a word line installed in parallel to a row. A drain electrode of the switching transistor is connected to a bit line installed in parallel to a column.
For example, when data stored in a certain memory cell is read out, it is necessary to activate a corresponding word line, i.e., to turn ON the switching transistor constituting the memory cell by applying an “H” (high) level voltage through the word line. This enables a detection of a rise or drop in voltages occurring on a corresponding bit line caused by an electric charge accumulated in the memory capacitor and the reading of one-bit data showing a “0” or “1” state.
On another hand, when data composed of the “1” state is written in a memory cell, for example, the electrical charge is accumulated in the above memory capacitor by activating the corresponding word line, i.e., by applying the “H” level voltage to the word line to turn the switching transistor ON and, at a same time, after the memory capacitor is charged by applying the “H” level voltage to the corresponding bit line, the switching transistor is turned OFF by applying a “L” (low) level voltage to the word line. Though the electrical charge accumulated in the memory capacitor is borne once therein, due to a minimal amount of leakage current, it decreases gradually as time elapses and is lost. It is, therefore, necessary to perform an operation called a “refresh” in which, after the switching transistor is turned ON every certain period of time, the electric charge being stored but gradually decreasing in the memory capacitor is detected and the detected charge is amplified by a sense amplifier, and then the same memory capacitor is again charged.
If the DRAM has several megabit capabilities, one memory cell array is sufficient. However, if it has several tens of megabits to several gigabit capabilities, a number of memory cells becomes several tens of thousands to several tens of billions, which causes inconveniences of processing enormous numbers of word lines and bit lines, longer access time for writing or reading data in and from a desired memory cell, or the like. To avoid this problem, the DRAM is ordinarily provided with a plurality of memory cell arrays. A part of the memory cell combined with a circuit mounted around the memory cell is called a “bank”. In the DRAM having a plurality of banks, the refreshing operation described above is performed using a counter called a “refresh counter” internally mounted by the following procedures. That is, in the DRAM having two banks, for example, a counter value of the refresh counter is renewed and two banks are alternately selected by least significant several bits. Then, in a selected bank, “H” level voltages are applied, in order, to a plurality of word lines based on the counter value and all switching transistors connected to the word lines are turned ON and, after the electric charge is produced by the switching transistors being in an ON state, the stored but gradually decreasing charge in the memory capacitor is amplified by the sense amplifier and the same memory capacitor is again charged.
In the above-described DRAM having the plurality of banks, a refresh counter test for checking whether the above refresh counter is operating normally or not is introduced as one of functions contained in specifications of the DRAM. In the refresh counter test, whether the refresh counter is operating normally or not is confirmed by writing, in order, specified data into each of the memory cells while data stored in all or a part of the memory cells is being refreshed, then by reading, in order, data written in each of the memory cells after completion of the refreshing operation and by checking if data written previously in each of the memory cells is correctly read. In this test, the ordinary refresh in which, as described above, the electric charge stored but gradually decreasing in the memory capacitor is amplified and then the same memory capacitor is again charged, is not used. The ordinary refresh is generally called “automatic refresh” or “self refresh” in which, once a command to execute the refreshing operation is entered from outside, the refreshing operation does not stop until the amplification of the charge stored but gradually decreasing in the memory capacitor is ended and until a stop command is executed.
In contrast, the refresh used in the refresh counter test is generally called a “CBR (Cas Before Ras) refresh”, in which, every time the command to execute the refresh is entered from outside, the counter value of the refresh counter is sequentially incremented to execute the refreshing operation.
A brief explanation of the refresh counter test is given below by referring to FIG.
14
and by using, as an example, a synchronous DRAM which is provided with banks A and B and a supplied command in synchronization with a clock from a CPU (Central Processing Unit), memory control unit or a like mounted externally and operates based on the supplied command.
First, in response to a mode register set command MRS (see (
2
) in
FIG. 14
) entered from outside in synchronization with the clock CLK (see (
1
) in FIG.
14
), contents stored in the mode register are changed to an operation code used to designate a refresh counter test mode obtained by decoding an address supplied from outside. A plurality of mode registers mounted around the bank is used to temporarily store a variety of information including a burst length showing a number of clocks in a burst mode to perform consecutive operations of writing and reading data the like operations and various operation codes used to designate the refresh counter test mode and the burst mode.
Next, in response to a refresh command REF (see (
2
) in
FIG. 14
) supplied from outside in synchronization with the clock CLK (see (
1
) in FIG.
14
), the counter value of the refresh counter is renewed. If a least significant bit RCL (see (
7
) in
FIG. 14
) of the counter value is, for example, a value RCLB to be used for activating the bank B, a signal RASB (see (
6
) in
FIG. 14
) is produced, based on the value RCLB, which activates a row decoder mounted corresponding to the bank B for applying the “H” level signal to a specified word line of the bank B by decoding an external row address supplied from outside or an internal row address composed of the counter value of the refresh counter. Therefore, since the row decoder corresponding to the bank B is activated by the signal RASB, the “H” level voltage is applied to the word line of the bank B designated by the row address and the refreshing is performed on the memory cell connected to the word line.
Then, in order to write specified data in the bank which has already been refreshed, it is necessary to designate the bank into which data is to be written and to activate a column switch which is a switch used to connect the bit line installed corresponding to the bank with an input/output line, installed in parallel to the bit line, adapted to input and/or

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