Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-08-09

2001-08-28

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S196000, C365S207000

Reexamination Certificate

active

06282142

ABSTRACT:

The present application claiming priority under 35 U.S.C. §119 to Japanese Application No. 11-290881 filed on Oct. 13, 1999, which is hereby incorporated by reference in its entirely for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, the present invention relates to a device suitable for applying to a dynamic type random access memory.
2. Description of the Related Art
A dynamic type random access memory (DRAM) is applied to various electronic products, such as an image data memory and a personal computer.
In recent years, such electronic products including DRAMs have been more and more required to operate at high speeds. Also, in order to realize such high speed operation, the DRAMs themselves are requested to operate at higher speed. A read operation which reads out data form memory cells of the DRAM is particularly required to be shortened.
In the case where the high speed operation of the DRAM is realized, it is desirable to avoid complicating the process to manufacture such a DRAM. Because as processes of the DRAM become complex, the cost of the DRAM becomes higher. It is also desirable to minimize the number of transistors used. This is because as the number of transistors is minimized, the size of the DRAM is reduced.
SUMMARY OF THE INVENTION
The first object of the invention is to provide a semiconductor memory device, such as a DRAM which functions of a high speed operation without complicating processes for the semiconductor memory device.
The second object of the invention is to provide such semiconductor device which is comprised of minimum transistors in order to reduce the size thereof.
To achieve the object, in a preferred embodiment of the invention, sense amplifiers are respectively located at both ends of bit line pair. These sense amplifiers amplify a voltage difference between the bit line pair in response to a sense amplifier active signal during a sensing period.
According to the present invention, since the voltage difference between the bit line pair are amplified at the both ends of the bit line pair, the time spent amplifying the voltage between the bit line pair may be shortened.


REFERENCES:
patent: 5917744 (1999-06-01), Kirihata et al.
patent: 6125071 (2000-09-01), Kohno et al.
patent: 6147918 (2000-11-01), Takashima et al.
patent: 6154402 (2000-11-01), Akita

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