Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
1999-08-12
2001-06-19
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S189090
Reexamination Certificate
active
06249477
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device using a double word line system and a negative voltage word line system.
2. Description of the Related Art
A demand for high integration of a memory cell is increasing with mass storage on a semiconductor memory device. To respond to the demand, a double word line system has been employed in which a sub-word line driving circuit is provided within a memory cell to divide a main word line composed of metal wiring into a plurality of sub-word lines consisting of polysilicon wiring so that the density of the word line is increased.
FIG. 9
is a block diagram showing a concept of the double word line system. Operations and approximate configurations of the word line system and its driving device in a semiconductor memory device using a double word line system are described hereafter by referring to FIG.
9
. Bit lines and their related parts are not shown in the drawing.
A memory cell array
100
of the semiconductor memory device shown in
FIG. 9
is provided with main row decoder circuits
101
1
,
101
2
and so on, and sub row decoder circuits
102
1
,
102
2
and so on. Any one of the main row decoder circuits
101
1
,
101
2
and so on is selected depending on an internal address signal and a row decoder control signal. For example, if the main row decoder circuit
101
1
is selected, the main word line MWL
0
connected to the main row decoder circuit
101
1
is activated. Any one of the sub row decoder circuits
102
1
,
102
2
and so on is selected depending on the internal address signal and the row decoder control signal. For example, if the sub row decoder circuit
102
1
is selected, it activates any one of the plural sub-word selection lines in accordance with the address signal. Each of sub-word line driving blocks
103
11
,
103
12
and so on has, for example, 4 sub-word line driving circuits and a sub-word line driving circuit selected by a sub-word selection line activates the sub-word line, for example, SWL
0
connected to the driving circuit.
The double word line system is used for the following reasons. When the word line is composed of polysilicon wiring, though its wiring pitch can be made small, because the polysilicon wiring is of high electrical resistance, wire delay time at the end of the wiring, if the wiring is long, is increased, thus causing the interference with the improvement of an operating speed of memory.
To solve this problem, the main word line is formed by using metal wiring, which is difficult to make its wiring pitch smaller but being of low electrical resistance, such as aluminum (Al) or the like, and a plurality of sub-word line driving blocks are provided within the memory array to connect memory cells using a short sub-word line extending from each of the sub-word line driving circuits. This enables an increase in word line density as well as in operating speed of memory.
Moreover, in the double word line system as shown in
FIG. 9
, by selecting the sub row decoder circuits in such a manner that one selected odd-numbered circuit is positioned in parallel with another selected odd-numbered circuit and one selected even-numbered circuit is positioned in parallel with another selected even-numbered circuit, the amount of data to be written and/or read can be increased accordingly.
FIG. 10
is a block diagram showing an example of configurations of a conventional semiconductor memory device. Slightly detailed configurations and operations of the conventional semiconductor memory device employing the double word line system are described below.
The conventional semiconductor memory device shown in
FIG. 10
is so figured that it approximately comprises a main row decoder
111
, a main word line
112
connected to the main row decoder
111
, a sub row decoder circuit
113
, a sub-word selection line
114
connected to the sub row decoder circuit
113
, more than one, for example, four sub-word line driving circuits
115
constituting one sub-word line driving block connected to the sub-word selection lines
114
, a sub-word line connected to each sub-word line driving circuit
115
, two or more memory cells
117
horizontally connected to each sub-word line
116
and a bit line
118
vertically connected to each memory cell
117
.
The main word line
112
is activated when the main row decoder circuit
111
is selected. Any one of the sub-word selection lines
114
is activated by the selection of the sub row decoder circuit
113
and, as a result, any one of the corresponding sub-word line driving circuits
115
is selected, which activates any one of the sub-word lines
116
connected to the selected sub-word line driving circuit
115
. On the other hand, a bit line
118
is activated by a column driving circuit selected (not shown).
A cell transistor QM of the cell memory connected to the activated sub-word line
116
and the activated bit line
118
is turned ON when the sub-word line
116
becomes high (i.e., at a boosted power source potential Vpp) and either of a high-level voltage (power source potential Vcc) or a low-level voltage (ground potential GND) of the bit line is written on a cell capacitor CM, one end of which is connected to a terminal with ½ Vcc. The charge written on the cell capacitor CM, while the sub-word line
116
is low (i.e., at a ground potential), is held in the OFF state by the cell transistor QM.
In the semiconductor memory cell shown in
FIG. 10
, a threshold voltage Vtn of the cell transistor QM constituting the memory cell
117
is higher than that of peripheral transistors in order to reduce a subthreshold leakage current. Because of this, it is necessary to apply a voltage being higher than “sum of the threshold voltage Vtn of the cell transistor QM and the written voltage Vcc” to the sub-word line
116
connected to a gate of the transistor QM at the time of writing on the memory cell
117
, and accordingly the boosted power source potential Vpp being higher than the power source potential Vcc is used as a high-level voltage of the sub-word line
116
.
On the other hand, in order to respond to a demand for lowering the voltage to be used, which is increasing with mass storage on a semiconductor, a control of the boosted power source potential Vpp to a lower level is required. To do this, it is necessary to more lower the threshold voltage of the cell transistor QM. To prevent the degradation of hold characteristics of the memory cell attributable to a leakage current generated when the cell transistor QM is OFF which is specifically caused by the lowered threshold voltage Vtn, a negative potential Vnb has come to be instead used as a low-level voltage of the sub-word line
116
. In this case, the negative voltage Vnb is conventionally fed by a power source having a voltage different from a substrate voltage. This is because the amount of currents consumed in the case of using the Vnb power source is large and there is a possibility of a great deal of noises caused by clutter at the Vnb potential and, accordingly, the Vnb power source has to be completely and electrically isolated from the Vbb power source to avoid adverse effects on the threshold voltage of the transistor.
FIG. 11
is a block diagram showing configurations of a word line driving system of a conventional semiconductor memory device.
FIG. 12
shows levels of signals inputted when a word line is activated in the conventional sub-word line driving circuit.
The conventional word line driving system, as depicted in
FIG. 11
, is approximately composed of a main row decoder
121
, a sub row decoder circuit
122
, a sub-word line driving circuit
123
and a negative potential generating circuit
124
.
As shown in
FIG. 12
, the main row decoder circuit
121
, when a main word line is selected, is adapted to cause the main word line MWL to be at a boosted power source Vpp in response to an internal address signal and a row decoder circuit control signal and, when the
Lam David
NEC Corporation
Nelms David
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