Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-09-27

2001-06-19

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030, C365S201000, C365S185230

Reexamination Certificate

active

06249479

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an operation mode suitable for test.
A semiconductor memory device generally comprises: a memory cell array having memory cells, for storing data, arranged in a matrix and divided into a plurality of blocks; a row decoder that accesses the memory cell array block by block; word lines used to read the data stored in the memory cells; bitlines on which the voltage or current corresponding to the data appears; a sense amplifier that amplifies and outputs the bitline voltage in a read operation and supplies the bitline voltage according to the writing data in a write operation, and so on.
Like all of the other products, semiconductor memory devices are tested for reliability and other factors. The cost required for a test depends on the time required for the test. To reduce the cost needed for the test, the test time must be shortened. To achieve this, a voltage has been applied to a plurality of memory cells and the peripheral circuits at the same time, thereby shortening the testing time.
A test for simultaneously rewriting the data in all memory cells is carried out by selecting all blocks and setting all word lines at the writing voltage. When there is a defective memory cell, however, a leakage current due to the defect is too large, so that the writing voltage level drops, sometimes making the simultaneous test impossible. Should this happen, making the block including the defective block unselected enables the memory cells in the other blocks to be tested simultaneously. In the conventional semiconductor memory device, however, since all blocks are selected or blocks are selected one by one, this causes the problem of having to select the blocks not including the defective memory cell one by one.
In the electrically rewritable nonvolatile semiconductor memory device (EEPROM) disclosed in ISSCC Digest of Technical Papers, pp. 128-129, Feb., 1995, a row decoder using only nMOS transfer gates is used. With the row decoder, in the selected state, a transfer gate turns on and a voltage is applied to a word line. In the unselected state, the transfer gate turns off and the word line is brought into the floating state.
When there is a leak in a bitline, the data in the memory cell is read erroneously. Such a defective bitline must be replaced with a redundancy bitline free from leak current. To do this, a check has to be made to see if there is any leak in the bitline. In the conventional semiconductor memory device, because a read operation is carried out with all blocks in the unselected state, a junction leak in the bitline contact can be sensed. When the word line in the floating state is short-circuited with the bitline, there is no leak, so that the short circuit cannot be sensed.
Furthermore, to improve the yield of the semiconductor memory device, redundancies are used to replace the defective column or defective row with a good one. Conventional redundancies have the following problem: when a column or row becomes defective in a test after the replacement, the chip becomes defective. Moreover, because a semiconductor memory device capable of storing multi-values has generally a long writing time, the time required for a rewriting test is also long.
As described above, in the conventional semiconductor memory device, when there is a defective block having a defective memory cell, it is impossible to test the simultaneous rewriting of the data in all memory cells by selecting all blocks and setting all word lines at the writing voltage. Moreover, when a check is made to see if there is any leak in the bitlines, a read operation is performed with all blocks in the unselected state, so that a junction leak in the bitline contacts can be sensed, but short circuit between the floating word lines and bitlines cannot be sensed.
There is also another problem: when the redundancy circuit for replacing a defective column or a defective row malfunctions, the chip becomes defective. In addition, because a semiconductor memory device capable of storing multi-values has generally a long writing time, the time required for a rewriting test is also long.
A semiconductor memory device comprises: a memory cell array having memory cells arranged in a matrix; word lines and bitlines for reading the data from the memory cells; and a sense amplifier and latch circuit. The sense amplifier and latch circuit senses the bitline voltage corresponding to the data in reading the data from the memory cells and outputs the voltage corresponding to the writing data in writing the data into the memory cells.
The manufacturing cost of semiconductor memory devices gets higher as the chip area increases and gets still higher as the testing time gets longer. In conventional semiconductor memory devices, to reduce the cost, not only the area of memory cells but also the area occupied by their peripheral circuits are made as small as possible. For instance, an attempt is made to reduce the area by causing more than one bitline to share a sense amplifier and latch circuit and thereby reducing the number of sense amplifier and latch circuits in the chip. To shorten the testing time, a method of selecting more than one bit simultaneously and writing the data in a test is employed.
When more than one bitline shares a sense amplifier and latch circuit, however, because only one bitline is connected to a single sense amplifier and latch circuit, of the memory cells selected by one word line, only the memory cell connected to one bitline per sense amplifier and latch circuit is selected. Therefore, in this case, although the circuit area decreases, the testing time increases to a value corresponding to the number of bitlines per sense amplifier and latch circuit, resulting in a small cost reduction.
In contrast, with a memory capable of storing multi-values, because a single memory cell has a memory capacity more than one bit, the cost can be reduced as compared with a conventional memory where a single memory cell has one bit. Since the logical values in the circuit are binary, more than one sense amplifier and latch circuit for reading and writing the data into and from the multi-valued memory cells is needed for one bitline. Therefore, in a semiconductor memory for storing multi-values, it is particularly necessary to cause more than one bitline to share a sense amplifier and latch circuit. In this case, too, the testing time increases to a value corresponding to the number of bitlines per sense amplifier and latch circuit, resulting in a small cost reduction.
As described above, in conventional semiconductor memory devices where more than one bitline share a sense amplifier and latch circuit, the time required for operation tests increases to a value corresponding to the number of bitlines per sense amplifier and latch circuit, which becomes the factor that prevents the manufacturing cost of semiconductor memory devices from decreasing.
BRIEF SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor memory device capable of shortening the time required for product testing and reducing the cost needed for the testing.
A semiconductor memory device according to a first aspect of the present invention employs the following structures:
(1) In a semiconductor memory device comprising a memory cell array with a plurality of blocks each having a plurality of memory cells arranged in a matrix, a plurality of address latch circuits provided so as to correspond to the blocks, and a row decoder that accesses the memory cell array block by block according to the latched state of the plurality of address latch circuits,
(1-1) A control circuit for accessing the memory cell array by latching all of the blocks into the selected state and then canceling the address latching of the predetermined block into the unselected state is further provided.
(1-2) The determined block canceled the address latching thereof includes a previously checked faulty block

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