Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-04-10

2001-08-28

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Sync/clocking

C365S230030

Reexamination Certificate

active

06282150

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device for outputting data at a high speed synchronized to a clock.
2. Description of the Related Art
In some semiconductor memory devices, data exchanges can take place during both rise and fall of the pulse signals of a system reference clock. This type of semiconductor memory device divides input/output data internally into two phases of the clock pulse, a rise phase and a fall phase, so that data in each phase are processed internally at twice the period of the external data period, thus enabling an apparently high internal processing speed to be consistent with highspeed serial data transfer.
FIG. 10
shows a schematic diagram of a conventional configuration of such a semiconductor memory device, in which serial data synchronized to a reference clock are processed through an input/output (i/o) pad
100
, which is for connection to an external environment. The reference clock is a system reference clock in the system including this semiconductor memory device. Serial data exchanged with the external environment are processed one bit at time at the rise and fall phases of each clock pulse in the memory device. In general, data processed during the rise phase of the pulses are called even data, and data processed during the fall phases of the pulses are called odd data (these expressions will be used in the following presentation).
A demultiplexer
101
separates serial write-data input via the i/o pad
100
into even data and odd data according to the system reference clock CLK. The demultiplexer
101
supplies even data to serial-parallel conversion circuits
102
-
1
e
,
102
-
2
e
, and odd data to serial-parallel conversion circuits
102
-
1
o
,
102
-
2
o.
Serial-parallel conversion circuits
102
-
1
e
,
102
-
2
e
and
102
-
1
o
,
102
-
2
o
supply parallel data outputs to respective write-amps
103
-
1
,
103
-
2
, which enter the data to respective memory cells in the memory cell arrays
104
-
1
,
104
-
2
. These serial-parallel conversion circuits and write-amps are controlled according to into which of the memory cell arrays the data are to be entered. When the data are to be entered into memory cell array
104
-
1
, only the serial parallel conversion circuit
102
-
1
e
,
102
-
1
o
and write-amp
103
-
1
are operated while, when the data are to be entered into memory cell array
104
-
2
, only the serial parallel conversion circuit
102
-
2
e
,
102
-
2
o
and write-amp
103
-
2
are operated.
Data output from the memory cell arrays
104
-
1
,
104
-
2
are amplified by respective data-amps
105
-
1
,
105
-
2
for amplifying data to be supplied to parallel-serial conversion circuits
106
-
1
e
,
106
-
2
e
and
106
-
1
o
,
106
-
2
o
. The output data are parallel data constituted by the even data and odd data entered by the write-amps, and even data are supplied to parallel-serial conversion circuits
106
-
1
e
,
106
-
2
e
while odd data are supplied to parallel-serial conversion circuits
106
-
1
o
,
106
-
2
o
. A multiplexer
107
-e selects and outputs even data output from parallel-serial conversion circuits
106
-
1
e
or
106
-
2
e
, while a multiplexer
107
-o selects and outputs odd data output from
106
-
1
o
or
106
-
2
o.
These data-amps, parallel-serial conversion circuits and multiplexers are controlled according to which of the memory cell arrays is to be used for reading the data. That is, when the data are to be read from the memory cell array
104
-
1
, only the data-amp
105
-
1
and the parallel-serial conversion circuits
106
-
1
e
and
106
-
1
o
are operated so that the multiplexers
107
-
e
,
107
-
o
select data output from the parallel-serial conversion circuits
106
-
1
e
,
106
-
1
o
and output those data respectively. On the other hand, when the data are to be read from the memory cell array
104
-
2
, only the data-amp
105
-
2
and the parallel-serial conversion circuits
106
-
2
c
and
106
-
2
o
are operated so that the multiplexers
107
-
e
,
107
-
o
select data output from the parallel-serial conversion circuits
106
-
2
e
,
106
-
2
o
and output those data respectively. Operational control for such read steps and above write steps is carried out by a control circuit (not shown) by supplying appropriate control or selection signals (for example, the selection signals “U/L” indicated in
FIG. 10
) according to read/write addresses.
A multiplexer
108
outputs even data from the multiplexer
107
-
e
during the rise phase of the system reference clock CLK, and outputs odd data from the multiplexer
107
-
o
during the fall phase of the system reference clock CLK. Output data from the multiplexer
108
are output externally from the i/o pad
100
.
According to such a device structure, when write-data are input into the i/o pad
100
, data are divided in the demultiplexer
101
into even data and odd data, and the divided data are supplied to the respective serial-parallel conversion circuits. If the specified write address is in the memory cell array
104
-
1
, inside the semiconductor memory device, even data are accepted by the serial-parallel conversion circuit
102
-
1
e
during the fall phases of the reference clock while odd data are accepted in the serial-parallel conversion circuit
102
-
1
o
during the rise phases of the reference clock. (It should be noted that, inside the memory device, there is no restriction regarding processing of even and odd data during the rise or fall phase of the clock pulse, so that such inversion of the timing of data exchange is allowable. Such method can be used for read-operations.) Accordingly, even data and odd data are converted to parallel-data, and are entered through the write-amp
103
-
1
into specific memory cells in the memory cell array
104
-
1
.
When the data are to be read, data from appropriate memory cells corresponding to read addresses are supplied to the data-amp. If the specified read address is in the memory cell array
104
-
1
, parallel even data and odd data from the memory cell array
104
-
1
are output to parallel-serial conversion circuits
106
-
1
e
,
106
-
1
o
through the data-amp
105
-
1
for conversion to serial data and the converted data are supplied to the multiplexers
107
-
e
,
107
-
o
. That is, even data are successively supplied to the multiplexer
107
-
e
while being synchronized to the fall phases of the reference clock, and odd data are successively supplied to the multiplexer
107
-
o
while being synchronized to the rise phases of the reference clock.
Then, multiplexers
107
-
e
,
107
-
o
select data from the respective parallel-serial conversion circuits
106
-
1
e
,
106
-
1
o
for outputting to the multiplexer
108
, which selects data alternately during the rise or fall of the system reference clock pulses for successive data output. Accordingly, highspeed serial data are output externally one bit at a time during either the rise or fall of the reference clock pulses from the i/o pad
100
. It should be noted that, in the memory cell array
104
-
2
, processes similar to those described for the memory cell array
104
-
1
are carried out for the read/write data.
In recent years, increased circuit density of LSI devices has caused the operational speed of CPU to increase so that the system clock now operates at a speed exceeding
400
MHz. In contrast, although the capacity of semiconductor memory device has been increased, the resulting increase in the length of internal lines (for example, word lines, bit lines, and the like) causes an increase in the duration of charging/discharging the lines, thus slowing the response speed of the memory device so that the operational speed cannot be improved to the extent achievable in CPU circuits. In such semiconductor memory devices, it is essential that the slower internal processes be made compatible with the faster external data i/o processes to compensate for the difference in the longer operational cycle of the internal devices and shorter cycles of the external

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