Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-12-21

2001-01-02

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000

Utility Patent

active

06169699

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and particularly to assignment of bank addresses in a multi-bank-structured semiconductor memory device. This application is based on Japanese Patent Application No. 10-367204, filed Dec. 24, 1998, the content of which is incorporated herein by reference.
Several conventional semiconductor memory devices adopt a DRAM (Dynamic Random Access Memory) and comprise an interface circuit capable of high-speed data transfer. Taking a 72M-bit multi-bank-structured DRAM as an example, explanation will now be made to conventional techniques and problems thereof.
In the 72M-bit multi-bank-structured DRAM shown in
FIG. 1
, an interface circuit
1
capable of high-speed data transfer and including a pad group is arranged in parallel with lateral edges at an end of a silicon chip having two longitudinal edges and two lateral edges. The interface circuit performs input of commands and input/output of data and power supply from an external power source, through the pad group. Also, the interface circuit
1
includes an access control circuit for controlling access with memory cell arrays.
Formed in the main parts of the chip are memory cell arrays
2
each having a 16-bank structure extended like a matrix in the row and column directions. The interface circuit
1
is arranged along the row direction in one side of the array.
As shown in
FIG. 1
, the memory cell array
2
has a structure in which cell array units
3
each consisting of a 9/8M-bit memory cell group arranged in a matrix of 16 rows×4 columns. A row decoder
4
is provided between adjacent columns of cell array units
3
.
Each column constructed by a plurality of cell array units
3
comprises 36 pairs of data lines
5
. The 36 pairs of data lines
5
are connected to 36 pairs of DQ buffers
6
. Therefore, the interface circuit
1
and the DQ buffers
6
arranged along the row direction of the memory cell array
2
are connected to each other by 144 pairs of data lines
5
a
(every 36 pairs are symbolized as a fat arrow). In this case, the data lines
5
a
include write lines and read lines or common write/read lines.
In addition, the DQ buffer is a circuit which operates to amplify and transfer data of the data line
5
during reading operation and also operates to drive the data line in accordance with the logic state of the data line
5
a
during writing operation.
One bank consists of one line of cell array units
3
, and bank addresses such as B
0
to B
15
are assigned to banks sequentially from the side closest to the interface circuit
1
. For example, if the bank address B
0
is selected, four cell array units hatched in FIG.
1
and DQ buffers corresponding thereto are activated simultaneously thereby enabling operation. Therefore, all the banks forming the memory cell array
2
can be accessed in total 16 cycles.
In this multi-bank-structured DRAM, the operation cycle is set to be high in order to realize a high-speed data transfer rate, and a large amount of data is exchanged with the memory cells designated to the selected bank for every cycle. Therefore, the current dissipation is very large. In
FIG. 1
, data flow exchanged between cell array units of each column and the interface circuit
1
is indicated by a bi-directional arrow (data line
5
a
).
That is, the dissipated current consumed by the memory cell array
1
and subsidiary circuits thereof has come to be very large, e.g., the bit line restore (refresh) current is about 200 mA in case where a number of banks are sequentially activated in minimum cycles, and the dissipated current is about 250 mA in case where writing is sequentially performed in minimum cycles. Meanwhile, various subsidiary circuits, power source circuits, and pad groups are arranged closely in the interface circuit
1
and the peripheral portion thereof, thus making it very difficult to wire low-resistance power source lines with a sufficient line width therebetween.
For example, if normal operation should be guaranteed independently from the distance between the selected and activated banks and the power source pads when a power source voltage is supplied from an external power source connected to external terminals of a package through power source pads included in the pad groups, a large number of DQ buffers must be connected with pad groups through power lines having a low wiring resistance R, and a drop of the power source voltage due to an I*R drop and operation error of the memory cells caused by such a voltage drop must be avoided, with respect to a large current I dissipated by the memory cell array
2
, DQ buffers
6
, and control circuits thereof (not shown).
Therefore, the line width of the power lines must be enlarged throughout the narrow and long interface circuit
1
. If the line width of the power lines is thus enlarged, there is a problem that the chip size increases accordingly.
In addition, since several kinds of internal power source voltages are normally required to operate a multi-bank-structure DRAM, it is necessary to maintain a space for integrating internal power source generation circuits which generate several kinds of internal power source voltages, into the peripheral portion of the interface circuit
1
(or within the inside thereof).
However, internal power source generation circuits occupy a large area in proportion to the size of the dissipated current I, leading to a problem of increase the chip size. That is, the following problem has occurred to realize these specifications and functions.
(1) Since the dissipated current of the memory cell array and subsidiary circuits is very large, the resistance of power source lines must be reduced. Therefore, the line width of the power source lines must be increased, resulting in increase of the chip size.
(2) In each of internal potential generation circuits such as internal power source circuits which generates a bit-line restore potential, reading from memory cells, boosting potential generation circuits for restoring word lines, and the like, the size of control transistors must be increased in accordance with increase of the loading current, and increase of the line width and provision of additional circuits are required. As a result, the chip size is increased.
BRIEF SUMMARY OF THE INVENTION
As has been described above, in a conventional multi-bank-structured DRAM, since selected banks are arranged deviated in the upper (or lower) side of the interface circuit, the operation current of the selected banks becomes very large so that the line width of the power source lines must be increased or internal power source circuits must be added, involving a problem that the chip size is enlarged. If the integration level of the multi-bank-structured DRAM is increased more in the future and the number of banks increases, this problem will become more important.
The present invention has been made to solve the above problem and has an object of providing a multi-bank-structured DRAM capable of high-speed transfer without causing enlargement of the chip size due to increase of the line width of power source lines or addition of internal power source generation circuits.
The semiconductor memory device according to the present invention is characterized in that a plurality of cell array units forming each bank are assigned divisionally to cell array units in both sides of an interface circuit interposed therebetween, in forming a multi-bank-structured DRAM capable of high-speed data transfer.
The division of the cell array units forming one bank is characterized in that those cell array units that are situated at point-symmetrical positions with respect to the center of the interface circuit are selected and assigned to one same bank.
Specifically, a semiconductor memory device according to the present invention comprises an interface circuit having a first side and a second side along a lengthwise direction of the interface circuit, a first memory cell array placed along the first side of the interface circuit and having

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