Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-06-22

2001-06-12

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030, C365S222000

Reexamination Certificate

active

06246631

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device which can enable a double word line by using the fact that word lines of two blocks are enabled at the same time in a block set of
2
N rows during an NK refresh operation.
In an isolated cell capacitor, a data is stored in the form of electric charges. The electric charges stored in the cell capacitor become extinct by the leakage current. It is thus necessary to bring out, read and re-write the data before the data is completely extinguished. This is called a refresh operation.
The refresh operation is performed by varying a row address strobe signal/RAS from high to low, turning on a word line corresponding to a row address, and enabling a sense amp. Accordingly, all the cells connected to one word line are refreshed at the same time.
The refresh operation of the DRAM is carried out by one cycle of externally receiving a refresh address and dropping and raising the RAS signal/RAS. A refresh cycle indicates the number of the cycles selecting all the rows of the DRAM and finishing the refresh operation. That is, the refresh cycle indicates how many word lines must be enabled to refresh all cells of the DRAM.
The conventional memory device such as the DRAM is so designed that its refresh cycle can simultaneously support the NK and
2
NK refresh operations, and is processed according to a bonding option. After fabricated, the memory device is used on a board where the NK refresh operation is supported or a board where the
2
NK refresh operation is supported. In general, in the case of the
2
NK refresh operation, the memory device is processed according to the “H” bonding option, and in the case of the NK refresh operation, the memory device is processed according to the “L” bonding option.
The conventional memory device always performs an access operation (namely, read/write) according to the
2
NK refresh operation, regardless of the refresh cycle.
FIG. 1
is a block diagram showing addresses of a row path of the conventional semiconductor memory device performing the NK refresh operation.
A first buffer
10
receives and buffers a block set division address ADD_
2
NK and a row active refresh mode designating signal NK_REFRESHB, a second buffer
12
receives and buffers a block selection address ADD_BLOCK, and a third buffer
14
receives and buffers a word line selection address ADD_WL for selecting one word line from a cell array in the selected block.
When the refresh mode designating signal NK_REFRESHB is at a low level, output signals ADDX_
2
NK, ADDXB_
2
NK from the first buffer
10
are compressed and fixed to a high level. The fixed signals are re-buffered in a fourth buffer
16
with output signals ADDX_BLOCK, ADDXB_BLOCK from the second buffer
12
, and inputted to a block control unit
20
. The block set division address ADD_
2
NK is compressed in the block control unit
20
, and thus two of the
2
N blocks (B; set of cell arrays) are selected. Output signals ADDX_WL, ADDXB_WL from the third buffer
14
are re-buffered in a fifth buffer
18
, decoded by a decoder
22
and inputted to the two selected blocks B.
Accordingly, a bit line sense amp BL S/A and a bit line are connected by corresponding bit line sense amp control units CTRL_
1
~CTRL_
2
n+1 in the two selected blocks B. The word lines existing on the cell arrays
24
a
,
24
b
,
24
c
,
24
d
in the two blocks B are enabled by main word line driving units MWL_
1
~MWL_
2
n.
FIG. 2
is a block diagram illustrating the address ADD_
2
NK for dividing the whole cell array into two in the conventional
2
NK block set. The conventional
2
NK block set consists of two
1
NK block sets, and the respective cell arrays
0
~N include K word lines. The most significant bit of the addresses
00
. . .
00
~
11
. . .
11
for respectively designating the cell arrays is the address ADD_
2
NK which divides the whole cell array into two in the
2
NK block set and which is compressed during the NK refresh operation. On the other hand, the addresses except for the most significant bit become the block selection addresses ADD_BLOCK. An upper cell array and a lower cell array are selected at the same time by the identical block selection address ADD_BLOCK in the block set which is divided into an upper NK block set and a lower NK block set due to the address ADD_
2
NK compressed during the NK refresh operation.
As described above, in the case that the NK refresh operation and the
2
NK refresh operation are implemented in one memory device and the NK refresh operation is performed by the bonding option, any of the row addresses is not used, and the number of the word lines to be enabled during the read/write operation is increased by two times. As a result, the current consumption of the row path is increased by two times during the access operation, as compared with the semiconductor memory device performing the
2
NK refresh operation.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor memory device having an NK refresh cycle, which can lower an enable speed of a word line by reducing a resistance and a capacitance of the word line enabled during an access operation by using a redundant row address.
In order to achieve the above-described object of the present invention, there is provided a semiconductor memory device having a block set consisting of a plurality of blocks which are aligned in a vertical direction and which consist of a plurality of cell arrays aligned in a horizontal direction, including: a unit for receiving and buffering a block set division address, a refresh mode designating signal and a refresh request signal; a unit for receiving the block set division address to be compressed among the output signals from the buffering unit and a block selection address, and selecting one of the plurality of blocks; a unit for decoding modified signals outputted from the buffering unit, and selecting a right-side or left-side cell array group of a main word line having a double word line structure from the selected block; and a unit for buffering and decoding word line selection address signals, and driving a corresponding main word line, the block set being divided into the identical number of the cell array groups symmetrically from a sub-word line driver positioned at the centers of each block, the right-side cell array groups and the left-side cell array groups being connected respectively to the main word line driving units through the different main word lines.


REFERENCES:
patent: 4393476 (1983-07-01), Ong
patent: 5243557 (1993-09-01), Maeda et al.
patent: 5313423 (1994-05-01), Sato et al.
patent: 5414660 (1995-05-01), Sugibayashi et al.
patent: 5416748 (1995-05-01), Fujita
patent: 5539698 (1996-07-01), Suzuki
patent: 5596542 (1997-01-01), Sugibayashi et al.
patent: 5864496 (1999-01-01), Mueller et al.
patent: 5889712 (1999-03-01), Sugibayashi
patent: 6038634 (2000-03-01), Ji et al.
patent: 6049502 (2000-04-01), Cowles et al.
patent: 6064605 (2000-05-01), Muranaka et al.
patent: 6064619 (2000-05-01), Ahn et al.

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2498573