Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-09-18

2001-05-01

Phan, Trong (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

Reexamination Certificate

active

06226220

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a static random access memory improved in high speed reading and writing operations with a reduced hardware scale necessary for column selecting operation.
FIG. 1
is a diagram illustrative of a first conventional semiconductor memory device. The first conventional semiconductor memory device has a (M-row×N-column) array of memory cells
104
(
1
,
1
), - - -
104
(
1
,N), - - -
104
(M,
1
), - - -
104
(M,N), wherein N and M are the natural numbers. Word lines
106
(
1
),
106
(
2
), - - -
106
(M) extend in parallel to a row direction, wherein each of the word lines
106
(
1
),
106
(
2
), - - -
106
(M)
106
(M) is connected to the memory cells
104
(i,
1
),
104
(i,
2
), - - -
104
(i,N) which are aligned in the row direction along the each of the word lines
106
(
1
),
106
(
2
), - - -
106
(M), where 1≦i≦M. Plural pairs of bit lines
105
a
(
1
),
105
b
(
1
),
105
a
(
2
),
105
b
(
2
), - - -
105
a
(N) and
105
b
(N) extend in parallel to a column direction perpendicular to the row direction, wherein each pair of the bit lines
105
a
(
1
),
105
b
(
1
),
105
a
(
2
),
105
b
(
2
), - - -
105
a
(N) and
105
b
(N) is connected to the memory cells
104
(
1
,j),
104
(
2
,j), - - -
104
(M,j) which are aligned in the column direction along the each pair of the bit lines
105
a
(
1
),
105
b
(
1
),
105
a
(
2
),
105
b
(
2
), - - -
105
a
(N) and
105
b
(N), where 1≦j≦N. Plural column selecting circuits
501
(
1
),
501
(
2
), - - -
501
(N) are provided, so that each of the column selecting circuits
501
(
1
),
501
(
2
), - - -
501
(N) is connected to one pair of the bit lines
105
a
(
1
),
105
b
(
1
),
105
a
(
2
),
105
b
(
2
), - - -
105
a
(N) and
105
b
(N). For example, the column selecting circuit
501
(j) is connected to the one pair of the bit lines
105
a
(j) and
105
b
(j). The plural column selecting circuits
501
(
1
),
501
(
2
), - - -
501
(N) are operated to optionally select one pair of the bit lines
105
a
(
1
),
105
b
(
1
),
105
a
(
2
),
105
b
(
2
), - - -
105
a
(N) and
105
b
(N). A sense amplifier
102
is provided which is connected with single-paired read operating common bit lines
504
a
and
504
b
which are further connected through of the plural column selecting circuits
501
(
1
),
501
(
2
), - - -
501
(N) to the all pairs of the bit lines
105
a
(
1
),
105
b
(
1
),
105
a
(
2
),
105
b
(
2
), - - -
105
a
(N) and
105
b
(N). The sense amplifier
102
is made conductive to the selected one pair of the bit lines
105
a
(
1
),
105
b
(
1
),
105
a
(
2
),
105
b
(
2
), - - -
105
a
(N) and
105
b
(N) selected by the plural column selecting circuits
501
(
1
),
501
(
2
), - - -
501
(N). A write driver
103
is also provided which is connected with single-paired write operation common bit lines
505
a
and
505
b
which are further connected through of the plural column selecting circuits
501
(
1
),
501
(
2
), - - -
501
(N) to the all pairs of the bit lines
105
a
(
1
),
105
b
(
1
),
105
a
(
2
),
105
b
(
2
), - - -
105
a
(N) and
105
b
(N). The write driver
103
is also made conductive to the selected one pair of the bit lines
105
a
(
1
),
105
b
(
1
),
105
a
(
2
),
105
b
(
2
), - - -
105
a
(N) and
105
b
(N) selected by the plural column selecting circuits
501
(
1
),
501
(
2
), - - -
501
(
19
. Each
501
(j) of the plural column selecting circuits
501
(
1
),
501
(
2
), - - -
501
(N) further comprises a first n-channel MOS field effect transistor MN(j), a first p-channel MOS field effect transistor MP(j), a second n-channel MOS field effect transistor MNB(j), and a second p-channel MOS field effect transistor MPB(j). The first n-channel MOS field effect transistor MN(j) is connected in series between the write operating common bit line
505
a
connected to the write driver
103
and one bit line
105
a
(j) of the selected bit lines
105
a
(j) and
105
b
(j) in the selected pair. The first n-channel MOS field effect transistor MN(j) turns ON to allow a write operation to be carried out by the write driver
103
to transmit data through the bit line
105
a
(j). The first p-channel MOS field effect transistor MP(j) is connected in series between the read operating common bit line
504
a
connected to the sense amplifier
102
and the one bit line
105
a
(j) of the selected bit lines
105
a
(j) and
105
b
(j) in the selected pair The first p-channel MOS field effect transistor MP(j) turns ON to allow a read operation to be carried out by the sense amplifier
102
to transmit data from the memory cell through the bit line
105
a
(j) to the sense amplifier
102
. The second n-channel MOS field effect transistor MNB(j) is connected in series between the write operating common bit line
50
b
connected to the write driver
103
and another bit line
105
b
(j) of the selected bit lines
105
a
(j) and
105
b
(j) in the selected pair. The second n-channel MOS field effect transistor MNB(j) turns ON to allow a write operation to be carried out by the write driver
103
to transmit data through the bit line
105
b
(j). The second p-channel MOS field effect transistor MPB(j) is connected in series between the read operating common bit line
504
b
connected to the sense amplifier
102
and the other bit line
105
b
(j) of the selected bit lines
105
a
(j) and
105
b
(j) in the selected pair. The second p-channel MOS field effect transistor MPB(j) turns ON to allow a read operation to be carried out by the sense amplifier
102
to transmit data from the memory cell through the bit line
105
b
(j) to the sense amplifier
102
. Read operation column selecting lines
502
(
1
),
502
(
2
), - - -
502
(N) are provided which extend in the row direction, wherein each
502
(j) of the read operation column selecting lines
502
(
1
),
502
(
2
), - - -
502
(N) is connected to the first and second p-channel MOS field effect transistors MP(j) and MPB(j) of the corresponding column selecting circuit
501
(j) One of the read operation column selecting lines
502
(
1
),
502
(
2
), - - -
502
(N) is selected to turn ON the paired first and second p-channel MOS field effect transistors MP(j) and MPB(j), whereby the paired bit lines
105
a
(j) and
105
b
(j) are made conductive through the column selecting circuit
501
(
1
) to the sense amplifier
102
for allowing the sense amplifier
102
to perform the reading operation. Write operation column selecting lines
503
(
1
),
503
(
2
), - - -
503
(N) are provided which extend in the row direction, wherein each
503
(j) of the write operation column selecting lines
503
(
1
),
503
(
2
), - - -
503
(N) is connected to the first and second n-channel MOS field effect transistors MN(j) and MNB(j) of the corresponding column selecting circuit
501
(j). One of the write operation column selecting lines
503
(
1
),
503
(
2
), - - -
503
(N) is selected to turn ON the paired first and second p-channel MOS field effect transistors MN(j) and MNB(j), whereby the paired bit lines
105
a
(j) and
105
b
(j) are made conductive through the column selecting circuit
501
(j) to the write driver
103
for allowing the write driver
103
to perform the writing operation.
The following description will focus on the read out operation for reading out data from the selected memory cell (i, j). The word line
106
(i) is activated to cause that data of the memory cells
104
(i,
1
), - - -
104
(i, N) connected to the activated word line
106
(i) are transmitted on all pairs of the bit lines
105
a
(
1
),
105
b
(
1
),
105
a
(
2
),
105
b
(
2
), - - -
105
a
(N) and
105
b
(N). Concurrently, the read operating column selecting line
502
(j) is selected to become low potential, so that the first and second p-channel MOS field effect transistors MP(j) and MPB(j) of the column selecting circuit
501
(j) connected to the selected read operating column selecting line
502
(j) turn ON, whereby the paired bit lines
105
a
(j) and
105
b
(j) are made electrically conducive through the read

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