Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1989-10-19

1991-05-21

Clawson, Jr., Joseph E.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365185, 307449, 307451, 307463, G11C 11409

Patent

active

050181076

ABSTRACT:
A semiconductor memory device has a decoder circuit. The decoder circuit includes a load transistor T.sub.1, a NAND gate circuit, i.e., a driver circuit serially connected to the load transistor T.sub.1 and includes a plurality of driving transistors T.sub.2 to T.sub.5 serially connected each other. An inverter IV is connected to the node N.sub.1 formed between the load transistor T.sub.1 and the NAND gate circuit. An additional load current increasing device T.sub.8 is connected to the node N.sub.1 or to a contact portion formed between two transistors arranged adjacently to each other in the NAND gate circuit. The load current increasing device T.sub.8 is operable only in the reading mode for increasing the load current and thus to increase the threshold voltage level of the decoder circuit up to about V.sub.cc /2, thereby preventing erroneous operation of the decoder and the memory cell array.

REFERENCES:
patent: 4247921 (1981-01-01), Itoh et al.
patent: 4645952 (1987-02-01), Van Tran
patent: 4649521 (1987-03-01), Tsuchida et al.
patent: 4710900 (1987-12-01), Higuchi
patent: 4782247 (1988-11-01), Yoshida
patent: 4893282 (1990-01-01), Wada et al.

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