Static information storage and retrieval – Associative memories – Ferroelectric cell
Utility Patent
2000-02-01
2001-01-02
Elms, Richard (Department: 2824)
Static information storage and retrieval
Associative memories
Ferroelectric cell
C365S149000
Utility Patent
active
06169684
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a hybrid semiconductor memory device, in which two types of memories with dissimilar functions are integrated together on the same semiconductor chip.
In a known semiconductor memory device, an array of memory cells, each including a transistor and a data storage capacitor that is connected to the source of the transistor, is formed on a semiconductor chip.
A conventional semiconductor memory device like this has the following drawbacks. Firstly, the random access speed of such a device is delimited by the performance of the memory cells. Secondly, although an external cache memory should be additionally provided for the device to improve the overall system performance thereof, the size of the system increases in such a case, thus raising the overall system cost correspondingly.
To solve these problems, a hybrid semiconductor memory device, in which an SRAM cache memory and a DRAM main memory are integrated together on a single semiconductor chip, was proposed in IEEE Journal of Solid State Circuits Vol. 27, No. 11, pp. 1534-1539, November 1992.
However, such a semiconductor memory device, which includes, on a single chip, two types of memories with dissimilar functions, e.g., the SRAM cache and DRAM main memories, occupies a greater area. This is because the size of an SRAM is about 10 times larger than that of a DRAM.
In addition, since the SRAM and DRAM have mutually different memory cell constructions, the layout and design processes of such a cache/main memory hybrid device become too complicated.
SUMMARY OF THE INVENTION
An object of the present invention is reducing the area of a hybrid semiconductor memory device including two types of memories with dissimilar functions on a single chip.
Another object of the present invention is simplifying the layout and design processes of such a memory device.
To achieve these objects, a semiconductor memory device according to the present invention includes first and second memory arrays integrated together on a single semiconductor chip. The first memory array is made up of memory cells of a first type, while the second memory array is made up of memory cells of a second type. Each said memory cell of the first type includes: first and second transistors, the sources of which are connected together; and a first data storage capacitor, one of two electrodes of which is connected to the source. Each said memory cell of the second type includes: a third transistor; and a second data storage capacitor connected to the source of the third transistor. The first memory array includes: a first bit line connected to respective drains of the first transistors; and a second bit line connected to respective drains of the second transistors. The second memory array includes: a third bit line connected to respective drains of the third transistors; and a fourth bit line, which is connected to respective drains of fourth transistors and is paired with the third bit line. Each said fourth transistor is adjacent to associated one of the third transistors. The first and second bit lines are parallel to each other. The third and fourth bit lines are parallel to each other. And a pitch defined between the first and second bit lines is equal to a pitch defined between the third and fourth bit lines.
In the semiconductor memory device according to the present invention, in which first and second memory arrays with dissimilar functions are integrated together on a single semiconductor chip, each memory cell belonging to the first memory array includes: first and second transistors, the sources of which are connected together; and a first data storage capacitor, one of two electrodes of which is connected to the source. Thus, the area occupied by the first memory array, and the overall area of the semiconductor memory device, can be greatly reduced. In addition, the semiconductor memory device is accessible at a far higher speed and the storage capacity thereof can be much increased.
Also, in the semiconductor memory device according to the present invention, a pitch defined between the first and second bit lines in the first memory array is equal to a pitch defined between the third and fourth bit lines in the second memory array. Thus, although first and second memory arrays with mutually different functions are integrated together on the same semiconductor chip, the interconnection layout can be simplified, so is the fabrication process thereof.
In one embodiment of the present invention, the memory device may further include: a first sense amplifier with one terminal connected to the first bit line; a second sense amplifier with one terminal connected to the second bit line; a third sense amplifier with one terminal connected to the third bit line; and means for transferring data from the first to second memory array, or vice versa. The transfer means includes first and second data transfer lines. The first data transfer line is preferably connected to the one terminal of the first sense amplifier and to the one terminal of the third sense amplifier via respective switches. The second data transfer line is preferably connected to the other terminal of the second sense amplifier and to the other terminal of the third sense amplifier via respective switches.
In such an embodiment, the first and second data transfer lines can be placed in parallel to each other. In addition, the first and second data transfer lines and the first, second and third bit lines can all be placed in parallel to each other. Accordingly, even though this memory device includes the means for transferring data between the first and second memory arrays with mutually different functions, the interconnection layout can be simplified.
In another embodiment, the first memory array may be implemented as cache memory core, and the second memory array may be implemented as main memory core.
In such an embodiment, the operating speed and storage capacity of a cache/main memory hybrid device can be both increased and yet the layout thereof can be simplified.
In an alternative embodiment, the first memory array may be implemented as register core, and the second memory array may be implemented as main memory core.
In such an embodiment, the operating speed and storage capacity of a register/main memory hybrid device can be both increased and yet the layout thereof can be simplified.
In still another embodiment, the memory device may further include: a first complementary bit line paired with the first bit line; a second complementary bit line paired with the second bit line; a first sense amplifier with one terminal connected to the first bit line and the other terminal connected to the first complementary bit line; and a second sense amplifier with one terminal connected to the second bit line and the other terminal connected to the second complementary bit line. The first complementary bit line and the first bit line preferably extend from the first sense amplifier in mutually opposite directions, and the second complementary bit line and the second bit line preferably extend from the second sense amplifier in mutually opposite directions.
In such an embodiment, the bit lines can be arranged according to an open configuration. Thus, the first array of memory cells of the first type, each including two transistors and one capacitor, can get its layout simplified.
In still another embodiment, the memory device may further include: a first word line connected to respective gates of the first transistors; a second word line connected to respective gates of the second transistors; a third word line connected to respective gates of the third transistors; and a fourth word line connected to respective gates of the fourth transistors. The first and second word lines are preferably parallel to each other. The third and fourth word lines are preferably parallel to each other. And a pitch defined between the first and second word lines is preferably equal to a pitch defined between the third and fourth word lines.
In such an embodiment,
Agata Masashi
Fujita Tsutomu
Kuroda Naoki
Takahashi Kazunari
Elms Richard
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Phung Anh
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