Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-06-29

2001-08-07

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Hardware for storage elements

C365S063000

Reexamination Certificate

active

06272034

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Background Art
The DRAM (Dynamic Random Access Memory) is conventionally known widely as one example of a semiconductor memory device. The DRAM includes a memory block where memory cells that are generally storage elements are formed and a peripheral circuit portion where a peripheral circuit which controls the operation of memory cells is formed. If four memory blocks are provided to a conventional DRAM, for example, the peripheral circuit portion has a cross shape. A problem of this conventional DRAM is that signal delay between each memory block and the peripheral circuit portion is not uniform.
According to a layout proposed for solving the problem above, the peripheral circuit portion is concentrated in the central portion surrounded by a plurality of memory blocks. One example of such a layout is shown in FIG.
10
.
Referring to
FIG. 10
, a chip (DRAM)
1
includes eight (8) memory blocks
7
a
-
7
h
formed on a main surface of a semiconductor substrate
2
, and a control circuit portion
3
arranged at a central portion surrounded by the memory blocks. Control circuit portion
3
corresponds to the peripheral circuit portion described above. The length of signal interconnection lines can be made uniform easily by placing memory blocks
7
a
-
7
h
around control circuit portion
3
, and signal delay between control circuit portion
3
and memory blocks
7
a
-
7
h
can be made uniform.
However, the DRAM shown in
FIG. 10
also has a following problem.
The conventional DRAM was not required to achieve a high speed operation which necessitates provision of any heat radiation member. Therefore, it was enough to dissipate heat from a package or a lead frame. As operating frequency of the recent MPU is enhanced, a DRAM operating at a high frequency of 100 MHz or more is required. In this case, generation of heat per unit area at the central portion of chip
1
increases compared with the conventional DRAM, since control circuit portion
3
including any circuit which generates much heat is concentrated in the central portion of chip
1
. Consequently, heat is not sufficiently radiated to cause thermal destruction.
If functions of the MPU, Cache, BIST (Built In Self Test) circuit, DRAM for parity and the like can be added after chip
1
is formed, various functions can be added to chip
1
of one type. However, if the structure shown in
FIG. 10
is used, those functions as described above cannot be added onto chip
1
selectively since chip
1
is not provided with any pad for interconnection between chips.
Redundancy repair means are respectively provided to memory blocks
7
a
-
7
h.
However, if any one of memory blocks
7
a
-
7
h
has a defect which cannot be repaired by the redundancy repair means, the entire chip
1
is determined to be a defective product even if remaining memory blocks are acceptable ones. If the memory block which cannot be repaired can be replaced with an acceptable one, redundancy repairing of chip
1
is possible to improve yield. However, the whole chip
1
is conventionally formed on a single semiconductor chip, and the redundancy repairing of the chip was impossible. As a result, the yield is decreased.
SUMMARY OF THE INVENTION
The present invention is made to solve such problems as described above. One object of the present invention is to provide a semiconductor memory device by which heat of a control circuit portion can be efficiently radiated when the control circuit portion is arranged to be surrounded by memory blocks.
Another object of the present invention is to provide a semiconductor memory device to which functions of MPU and the like can be selectively added.
Still another object of the present invention is to provide a semiconductor memory device by which yield can be improved.
A semiconductor memory device according to one aspect of the invention includes a plurality of memory blocks, a control circuit portion, and a heat radiation member. A plurality of memory cells are formed in each of the memory blocks. The control circuit portion is surrounded by the plurality of memory blocks, and includes a control circuit formed therein which controls operations of the memory cells. The heat radiation member is selectively placed on at least one of a front surface and a back surface of the control circuit portion, and has a function of radiating heat generated at the control circuit portion. The control circuit portion may be arranged to make signal delay between each memory block and the control circuit portion uniform.
Heat can be externally radiated from a portion where much heat is generated by selectively placing the heat radiation member on at least one of the front surface and the back surface of the control circuit portion. Consequently, an efficient heat radiation as well as reduction of cost are achieved compared with a case in which the heat radiation member is placed on the entire surface of the chip.
The semiconductor memory device as described above may be provided with a package. In this case, the heat radiation member preferably protrudes outward through the package. The package herein refers to any insulating member for forming an airtight seal of the chip.
Heat generated at the control circuit portion can be directly radiated from the package outward since the heat radiation member penetrates the package. As a result, an efficient heat radiation is achieved.
A semiconductor memory device according to another aspect of the present invention includes a first chip and a second chip. The first chip includes a plurality of memory blocks and a control circuit portion. A plurality of memory cells are formed in each of the plurality of memory blocks. The control circuit portion is surrounded by the plurality of memory blocks, and a control circuit which controls operations of memory cells is formed in the control circuit portion. A bump electrode is formed around the control circuit. The second chip is connected to the first chip via the bump electrode and arranged above the control circuit portion.
Functions of the MPU, Cache, BIST circuit, DRAM for parity and the like can be selectively added easily to the second chip which is separate from the first chip. By connecting the second chip to the first chip via the bump electrode, the functions described above of the MPU and the like can be selectively added to the semiconductor memory device which is, for example, a DRAM.
A bonding pad may be formed at a front surface of the second chip. Further, any heat radiation member for radiating heat generated at the control circuit portion or the second chip may be placed on at least one of the front surface of the second chip and a back surface of the control circuit portion.
By providing the second chip, the bonding pad can be formed easily on the front surface of the second chip. Consequently, a region where the bonding pad is formed is easily obtained. An efficient heat radiation becomes possible by providing the heat radiation member on at least one of the front surface of the second chip and the back surface of the control circuit portion.
According to still another aspect of the invention, a semiconductor memory device includes a plurality of memory block chips and a control circuit chip. A plurality of memory cells are formed at each of the memory block chips. The control circuit chip is surrounded by the memory block chips, and has a control circuit formed therein which controls operations of memory cells.
If, for example, one memory block chip is determined to be defective, only the defective memory block chip can be replaced with an acceptable memory block chip since the memory block chips and the control circuit chip are provided. Accordingly, a chip which must be discarded as defective is only a defective memory block chip, and yield can be improved compared with any conventional semiconductor memory device. An arbitrary number of memory block chips can be connected to the control circuit

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