Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1986-02-04

1988-03-08

Smith, Jerry

Excavating

371 21, 324 73R, G06F 1110

Patent

active

047303204

ABSTRACT:
A semiconductor memory device comprises a data input switching circuit (20) connected between the output side of a write check bit generating circuit (2) and the input side of a check bit memory cell array (32), a data output switching circuit (30) connected to the input side of an address decoder (9), and an address switching circuit (10) connected to the output side of the address decoder (9). When a test mode is entered, the data input switching circuit (2), data output switching circuit (30) and address switching circuit (10) connect a data input signal line (l), data output signal line (m) and address signal line (n), respectively, to the check bit memory cell array (32), enabling the check bit memory cell array (32) to be accessed from the outside.

REFERENCES:
patent: 4319356 (1982-03-01), Kocol
patent: 4359771 (1982-11-01), Johnson
patent: 4404519 (1983-09-01), Westcott
patent: 4502140 (1985-02-01), Proebsting
patent: 4523314 (1985-06-01), Burns
patent: 4531213 (1985-07-01), Scheuneman
patent: 4608669 (1986-08-01), Klara
"Error-Correcting Codes for Semicoductor Memory Applications: A State-of-the-Art Review", C. L. Chen et al, IBM J. Res. Develop., vol. 28, No. 2, Mar. 1984, pp. 124-134.
"Dynamic Testing of Memory Arrays Which Utilise ECC Logic", M. D. Quinn et al, Electronic Engineering, Mid-Mar. 1981, pp. 111-119.

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