Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1993-09-16

1995-04-04

Fears, Terrell W.

Static information storage and retrieval

Addressing

Plural blocks or banks

365200, 371 491, 371 493, G11C 1300

Patent

active

054043360

ABSTRACT:
The parity cell arrays are placed between the ordinary cell arrays and a second peripheral circuit. Data signal lines are provided between the ordinary cell arrays, between the ordinary cell arrays and the parity cell arrays, and between the parity cell arrays. These data signal lines are connected to read-write lines via data signal-line amplifier circuits. These data column-line amplifier circuits have almost the same construction. The data signal-line control circuit activates the data signal-line amplifier circuits during a write and a read operation to enable data transfer between the data signal lines and the read-write lines.

REFERENCES:
patent: 4660174 (1987-04-01), Takemae et al.
patent: 4679196 (1987-07-01), Tsujimoto
patent: 5089993 (1992-02-01), Neal et al.
patent: 5152492 (1992-08-01), Shimizu et al.
Nakano et al., "A Sub-100 ns 256K DRAM with Open Bit Line Scheme", IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, Oct. 1983, pp. 452-456.

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