Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1990-10-19

1993-07-27

Popek, Joseph A.

Static information storage and retrieval

Powering

365 51, G11C 1300, H01L 2710

Patent

active

052316076

ABSTRACT:
A semiconductor memory device has a memory cell array region, a plurality of signal lines arranged above the memory cell array region, and a plurality of power-supply lines or grounding lines, each of which has a first end and a second end and which are arranged between the signal lines in a similar pattern to that of the signal lines.

REFERENCES:
patent: 4525809 (1985-06-01), Chiba et al.
patent: 4695978 (1987-09-01), Itakura
patent: 5007025 (1991-04-01), Hwang et al.
Kou Wada and Kazumitsu Takeda, "Master-Slice Layout Design for Emitter Coupled Logic LSI", Review of the Electrical Communication Laboratories, vol. 26, No. 9-10, pp. 1355-1366 (Sep.-Oct. 1978).
L. W. Massengil and S. E. Diehi-Nagle, "Voltage Span Modeling for Very Large Memory Arrays", Nasecode IV, Proceedings of the Fourth International Conference on the Numerical Analysis of Semiconductor Device and Integrated Circuits, pp. 396-404 (Jun. 1985).
Peter W. Cook et al., ".mu.m MOSFET VLSI Technology: Part III--Logic Circuit Design Methodology and Applications, 3093 IEEE Trans. on Electron Devices", vol. ED-26, No. 4, pp. 333-334 (Apr. 1979).

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