Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1993-04-13

1994-06-21

Popek, Joseph A.

Static information storage and retrieval

Addressing

Sync/clocking

365206, 365191, G11C 11413

Patent

active

053233590

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates in general to static semiconductor memory devices, such as static RAM, and relates in particular to a memory device which performs stably even if noise is superimposed on the readout control signal.
2. Technical Background of the Invention
Semiconductor memory devices, such as static RAM, are known to utilize internal synchronization method to reduce the power consumption for its operation. The internal synchronization method is a method in which the peripheral circuits of the memory cells are operated, for each change in the address memory, only during a fixed interval of time based on a base pulse signal. This method requires an address change detection circuit ATD which detects a change in the address signal and generates the above mentioned base pulse signal.
Another technique belonging to the internal synchronization method aiming to further reduce the power consumption is known as a pulse drive method. This method is based on pulse driving of the circuits for a fixed time interval, such as word line connected to the memory circuit and the sense amplifier circuit connected to the word line for detecting the data read from the memory cells, in accordance with the base pulse signal generated by the address change detection circuit ATD. This method is referred to as the word line pulse driving method, or the auto power-down method, and is effective for reducing the power consumption of static RAM devices, for example.
FIG. 9 is a schematic circuit diagram for an example of the control circuit 10 using the auto power-down method for devices such as static RAM . This control circuit 10 is provided with pulse width amplifiers 30 and 40. The pulse width amplifier 30 receives the signal via a buffer 102, and outputs signals of pulse widths governed by the delay capacitances C1-C3. The pulse width amplifier 40 receives the signal via a buffer 123, and outputs signals of pulse widths governed by the delay capacitance C4.
The operation of the control circuit 10 for memory readout will be explained with reference to FIG. 10. When there is a change in the externally supplied address signal ADDRESS, then address change detection circuit ATD (not shown) generates a address change signal ATP.sub.1 -ATP.sub.n in accordance with this change. The address change signals ATP.sub.1 -ATP.sub.n are synthesized through the switching elements 1-13 shown in FIG. 9, and inputted into the control circuit 10. The signals are inputted into the pulse width amplifier 30 or 40, through the respective buffer 102 or 123, which generate control signals APD', ATDS' having amplified signal widths as illustrated in FIG. 10.
The control signals APD', ATDS' are used to control various signals which control the overall operations of the static RAM device. For example, the control signals APD', ATDS' along with write enable signals WE', WE and chip select signals CS', CS are inputted into the signal generation circuit shown in FIGS. 4 to 6, and generate signals SAON, DOC, LAT and LAT'. The signal generation circuit shown in FIG. 4 consists of a NAND gate 400 and a buffer 401, and generates a control signal SAON for controlling the ON-OFF actions of sense amplifier circuit 50 (to be explained later) in accordance with the signals WE', ATDS' and CS supplied thereto. The signal generation circuit shown in FIG. 5 consists of buffers 500, 503 and NAND gates 501, 502, and generates a signal DOC. The signal generation circuit shown in FIG. 6 consists of NAND gates 600, 601 and buffers 602, 603, and generate signal LAT, LAT'. The signals DOC, LAT, LAT' are used to control the operation of the data output circuit 60 (to be explained later) shown in FIG. 7. When reading out data from the memory cells, the signals WE' and CS are at the high level "H" while the signals WE, CS' are at the low level "L".
As shown in FIG. 10, when the address signal ADDRESS changes, the control signal APD' changes from the low level (henceforth referred to as the L level) to the high level (h

REFERENCES:
patent: 4707809 (1987-11-01), Ando
patent: 5228003 (1993-07-01), Tokuda

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2225669