Static information storage and retrieval – Interconnection arrangements
Patent
1994-01-13
1995-01-03
LaRoche, Eugene R.
Static information storage and retrieval
Interconnection arrangements
365 51, G11C 506
Patent
active
053792483
ABSTRACT:
A plurality of bit line signal IO lines L1, /L1 . . . Ln and /Ln are arranged on a memory cell array. These bit line signal IO lines are arranged to cross respective bit lines BL1, /BL1, . . . BLn and /BLn, and are connected to the corresponding bit lines, respectively. Each bit line signal IO line has an end extended to an end, in a direction perpendicular to the bit line, of a memory cell array, and is coupled at the end to a bit line peripheral circuit. Although bit line peripheral circuits could be arranged only at upper and lower ends of the bit lines in the prior art, the bit line peripheral circuits can be arranged also at the ends of the bit line signal IO lines in the invention. This can increase a degree of freedom in a layout for the bit line peripheral circuits, and thus the bit line peripheral circuits can be dispersedly arranged in a larger area.
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Anami Kenji
Murakami Shuji
Wada Tomohisa
LaRoche Eugene R.
Mitsubishi Denki & Kabushiki Kaisha
Zarabian A.
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